From: dinh.linux@gmail.com (Dinh Nguyen)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller
Date: Fri, 20 Feb 2015 01:15:21 -0600 [thread overview]
Message-ID: <54E6DF09.9060505@gmail.com> (raw)
In-Reply-To: <CAL_JsqKmbV69Q-hgnvnz-2+2T8k-Q+WcrFmewkfozKk06ZM7OA@mail.gmail.com>
Hi Rob,
On 2/19/15 12:13 PM, Rob Herring wrote:
> On Thu, Feb 19, 2015 at 11:06 AM, <dinguyen@opensource.altera.com> wrote:
>> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>>
>> By not having bit 22 set in the PL310 Auxiliary Control register (shared
>> attribute override enable) has the side effect of transforming Normal
>> Shared Non-cacheable reads into Cacheable no-allocate reads.
>>
>> Coherent DMA buffers in Linux always have a Cacheable alias via the
>> kernel linear mapping and the processor can speculatively load cache
>> lines into the PL310 controller. With bit 22 cleared, Non-cacheable
>> reads would unexpectedly hit such cache lines leading to buffer
>> corruption.
>
> You really should be doing this in your bootloader.
>
Can I ask what is your reasoning for doing this in the bootloader? It's
seems like this is such a nice mechanism to do it here.
Dinh
next prev parent reply other threads:[~2015-02-20 7:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-19 17:06 [RESEND PATCH 1/2] arm: socfpga: update l2 cache settings dinguyen at opensource.altera.com
2015-02-19 17:06 ` [RESEND PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller dinguyen at opensource.altera.com
2015-02-19 18:13 ` Rob Herring
2015-02-20 7:15 ` Dinh Nguyen [this message]
2015-02-20 13:53 ` Rob Herring
2015-02-20 13:57 ` Russell King - ARM Linux
2015-02-23 12:13 ` Pavel Machek
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