From: thunder.leizhen@huawei.com (leizhen)
To: linux-arm-kernel@lists.infradead.org
Subject: [Question] How can we support outer shareable on ARM64?
Date: Mon, 2 Mar 2015 16:02:12 +0800 [thread overview]
Message-ID: <54F41904.90303@huawei.com> (raw)
Hi,
Now, both cacheable memory shareability attribute and barrier are fixed to inner shareable. But
I afraid some hardware need outer shareable. If hardware support both inner and outer, do we need
to optimize?
for example(the code for now):
#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
#define smp_mb() dmb(ish)
How can we support both inner and outer shareable, or selectable?
Thanks
Zhen Lei
next reply other threads:[~2015-03-02 8:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-02 8:02 leizhen [this message]
2015-03-02 10:44 ` [Question] How can we support outer shareable on ARM64? Catalin Marinas
2015-03-03 2:32 ` leizhen
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