* [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
@ 2015-03-17 16:33 Gregory CLEMENT
2015-03-18 15:56 ` Gregory CLEMENT
2015-03-18 16:12 ` Thomas Petazzoni
0 siblings, 2 replies; 4+ messages in thread
From: Gregory CLEMENT @ 2015-03-17 16:33 UTC (permalink / raw)
To: linux-arm-kernel
For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-370.dtsi | 1 +
arch/arm/boot/dts/armada-xp.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 27397f151def..b38bfa03d3bf 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -129,6 +129,7 @@
compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
+ cache-level = <2>;
cache-unified;
wt-override;
};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 82917236a2fb..9806046dde1e 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -78,6 +78,7 @@
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
+ cache-level = <2>;
cache-unified;
wt-override;
};
--
2.1.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
2015-03-17 16:33 [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level Gregory CLEMENT
@ 2015-03-18 15:56 ` Gregory CLEMENT
2015-03-18 16:12 ` Thomas Petazzoni
1 sibling, 0 replies; 4+ messages in thread
From: Gregory CLEMENT @ 2015-03-18 15:56 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 17/03/2015 17:33, Gregory CLEMENT wrote:
> For L2 cache controller node, cache-level property is mandatory. Let's
> add it to Armada 370 and Armada XP device tree.
>
unless someone is against it, I will apply it on mvebu/dt tomorrow.
Thanks,
Gregory
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> arch/arm/boot/dts/armada-370.dtsi | 1 +
> arch/arm/boot/dts/armada-xp.dtsi | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
> index 27397f151def..b38bfa03d3bf 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -129,6 +129,7 @@
> compatible = "marvell,aurora-outer-cache";
> reg = <0x08000 0x1000>;
> cache-id-part = <0x100>;
> + cache-level = <2>;
> cache-unified;
> wt-override;
> };
> diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
> index 82917236a2fb..9806046dde1e 100644
> --- a/arch/arm/boot/dts/armada-xp.dtsi
> +++ b/arch/arm/boot/dts/armada-xp.dtsi
> @@ -78,6 +78,7 @@
> compatible = "marvell,aurora-system-cache";
> reg = <0x08000 0x1000>;
> cache-id-part = <0x100>;
> + cache-level = <2>;
> cache-unified;
> wt-override;
> };
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
2015-03-17 16:33 [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level Gregory CLEMENT
2015-03-18 15:56 ` Gregory CLEMENT
@ 2015-03-18 16:12 ` Thomas Petazzoni
2015-03-19 10:12 ` Gregory CLEMENT
1 sibling, 1 reply; 4+ messages in thread
From: Thomas Petazzoni @ 2015-03-18 16:12 UTC (permalink / raw)
To: linux-arm-kernel
Dear Gregory CLEMENT,
On Tue, 17 Mar 2015 17:33:54 +0100, Gregory CLEMENT wrote:
> For L2 cache controller node, cache-level property is mandatory. Let's
> add it to Armada 370 and Armada XP device tree.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thanks,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
2015-03-18 16:12 ` Thomas Petazzoni
@ 2015-03-19 10:12 ` Gregory CLEMENT
0 siblings, 0 replies; 4+ messages in thread
From: Gregory CLEMENT @ 2015-03-19 10:12 UTC (permalink / raw)
To: linux-arm-kernel
On 18/03/2015 17:12, Thomas Petazzoni wrote:
> Dear Gregory CLEMENT,
>
> On Tue, 17 Mar 2015 17:33:54 +0100, Gregory CLEMENT wrote:
>> For L2 cache controller node, cache-level property is mandatory. Let's
>> add it to Armada 370 and Armada XP device tree.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
applied on mvebu/dt with Thomas tag
Thanks,
Gregory
>
> Thanks,
>
> Thomas
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 4+ messages in thread
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2015-03-17 16:33 [PATCH] ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level Gregory CLEMENT
2015-03-18 15:56 ` Gregory CLEMENT
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2015-03-19 10:12 ` Gregory CLEMENT
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