From mboxrd@z Thu Jan  1 00:00:00 1970
From: ben.dooks@codethink.co.uk (Ben Dooks)
Date: Wed, 01 Apr 2015 17:01:41 +0100
Subject: [RESEND] Altera socfpga big endian work
In-Reply-To: <551C05CF.2000809@opensource.altera.com>
References: <1427282872-10563-1-git-send-email-ben.dooks@codethink.co.uk>
 <551AAB9D.1000809@opensource.altera.com> <551ABE7D.4090908@codethink.co.uk>
 <551ADDA0.5010500@opensource.altera.com> <551BCD77.6060906@codethink.co.uk>
 <551C05CF.2000809@opensource.altera.com>
Message-ID: <551C1665.6040509@codethink.co.uk>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On 01/04/15 15:50, Dinh Nguyen wrote:
> On 04/01/2015 05:50 AM, Ben Dooks wrote:
>> On 31/03/15 18:47, Dinh Nguyen wrote:
>>>
>>>
>>> On 3/31/15 10:34 AM, Ben Dooks wrote:
>>>> On 31/03/15 15:13, Dinh Nguyen wrote:
>>>>> Hi Ben,
>>>>>
>>>>> On 3/25/15 6:27 AM, Ben Dooks wrote:
>>>>>> This series enables the core of the socfpga systen to run in big endian
>>>>>> mode. It inclusdes support for debug uart, secondary core boot and has
>>>>>> support for timers and initial conversion patches for the mmc.
>>>>>>
>>>>>> The two drivers that are known to not work are the Ethernet and the
>>>>>> dwc2 usb. I do not have data for either, so I currently do not know
>>>>>> if it possible to change the hardware's endian fetch mode.
>>>>>>
>>>>>> The dwc2 driver on my cyclone5 socfpga board with v4.0-rc5 does not
>>>>>> work in little endian mode, which makes testing converting the driver
>>>>>> difficult. The supplied 3.10 kernel does work so it is not down to the
>>>>>> hardware. It detects the presence of a new device and then fails to
>>>>>> enumerate it (no other errors shown)
>>>>>>
>>>>>> This is up on git.baserock.org/delta/linux.git in the branch
>>>>>> baserock/bjdooks/socfpga-v5
>>>>>>
>>>>>> Sorry, this is a resend due to incorrect linux-arm-kernel mailing list
>>>>>> address.
>>>>>>
>>>>>
>>>>> I think I can take patches 1-3 through my tree, but the mmc patches
>>>>> [4-7] will need to linux-mmc tree.
>>>>
>>>> Thanks. I did CC 4-7 to the relevant maintainers.
>>>>
>>>> Any idea if dwc2 is going to be fixed before 4.1?
>>>>
>>>>
>>>
>>> I'll have to double check again, but I thought dwc2 on the socfpga has
>>> been work fine for quite some time now. What are the errors that you are
>>> seeing?
>>
>> With 4.0-rc5 it failed to enumerate a USB memory stick attached to
>> the board. It looked like VCC was supplied. We know the adapter is
>> working as it comes up under the default boot supplied on the board.
>>
> 
> Hmm...4.0-rc6's USB is working fine on my devkit:
> 
> socfpga_cyclone5 login: [   74.933518] usb 1-1: new high-speed USB
> device number 2 using dwc2
> [   75.144505] usb-storage 1-1:1.0: USB Mass Storage device detected
> [   75.150873] scsi host0: usb-storage 1-1:1.0
> [   76.154413] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra
>  1.26 PQ: 0 ANSI: 5
> [   76.164091] sd 0:0:0:0: [sda] 31266816 512-byte logical blocks: (16.0
> GB/14.9 GiB)
> [   76.172386] sd 0:0:0:0: [sda] Write Protect is off
> [   76.177645] sd 0:0:0:0: [sda] Write cache: disabled, read cache:
> enabled, doesn't support DPO or FUA
> [   76.194265]  sda: sda1
> [   76.198088] sd 0:0:0:0: [sda] Attached SCSI removable disk
> root
> root at socfpga_cyclone5:~# uname -a
> Linux socfpga_cyclone5 4.0.0-rc6-00009-g6c310bc #1 SMP Wed Apr 1
> 09:46:55 CDT 2015 armv7l GNU/Linux
> root at socfpga_cyclone5:~#
> 
> Attached is my defconfig...

Thanks, I will see if I can replicate this when I am back from the
mandatory holidays here.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius