From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 949BCC4332F for ; Tue, 8 Nov 2022 11:13:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9hmxc7vgcrS4d2IujiT9aWvTyBUnHbp0PUaNEj70Vmg=; b=qVbad3TRNM/rlK d9KjKuy2SDUGMK4I5W7El4zcVcLLXxBRbDCNzZDcemDmIApjDaLS64bd/XDPvnIXYKuEwxQke0hXQ Z2/zM+AdbH3gJU90/Br9g6nBTy8MZyZG0qDiHcNvShP7a+o6tsEXXdIP+IJF3PgcEqFaV8fOvgohM vpMhN+o0gzVgNoO4GmoubZJ2mJ4zqfi7kaDCpdyYIGHUA3eFJIzYnQjGokk1V0986QR5mlPXlWf8+ QJbUJfk7xPPqGZiGvs+EdwjgUAKnOejMm0QujP41ddoUo18DHW3ZWPXXmZXr+6XXTGCZ/UXuUEq2/ mjdNGbgW145OhzHdIoBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osMWR-004nDI-9K; Tue, 08 Nov 2022 11:12:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osMWN-004nAv-3O; Tue, 08 Nov 2022 11:12:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2C1F1424; Tue, 8 Nov 2022 03:12:02 -0800 (PST) Received: from [192.168.1.12] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6D56C3F534; Tue, 8 Nov 2022 03:11:53 -0800 (PST) Message-ID: <554c4bf5-8981-3d0e-6cd4-68fc854bcb09@arm.com> Date: Tue, 8 Nov 2022 12:11:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH 0/5] arch_topology: Build cacheinfo from primary CPU To: linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Len Brown , Sudeep Holla , Greg Kroah-Hartman , Gavin Shan , SeongJae Park , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, Jeremy Linton , Rob Herring References: <20221108110424.166896-1-pierre.gondois@arm.com> Content-Language: en-US From: Pierre Gondois In-Reply-To: <20221108110424.166896-1-pierre.gondois@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221108_031159_300731_64AA4CD9 X-CRM114-Status: GOOD ( 16.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + Rob Herring + Jeremy Linton On 11/8/22 12:04, Pierre Gondois wrote: > [1] and [2] build the CPU topology from the cacheinfo information for > both DT/ACPI based systems and remove (struct cpu_topology).llc_id > which was used by ACPI only. > > Creating the cacheinfo for secondary CPUs is done during early boot. > Preemption and interrupts are disabled at this stage. On PREEMPT_RT > kernels, allocating memory (and parsing the PPTT table for ACPI based > systems) triggers a: > 'BUG: sleeping function called from invalid context' [4] > > To prevent this bug, allocate the cacheinfo from the primary CPU when > preemption and interrupts are enabled and before booting secondary > CPUs. The cache levels/leaves are computed from DT/ACPI PPTT information > only, without relying on the arm64 CLIDR_EL1 register. > If no cache information is found in the DT/ACPI PPTT, then fallback > to the current state, triggering [4] on PREEMPT_RT kernels. > > Patches to update the arm64 device trees that have incomplete cacheinfo > (mostly for missing the 'cache-level' or 'cache-unified' property) > have been sent at [3]. > > Tested platforms: > - ACPI + PPTT: Ampere Altra, Ampere eMAG, Cavium ThunderX2, > Kunpeng 920, Juno-r2 > - DT: rb5, db845c, Juno-r2 > > [1] https://lore.kernel.org/all/20220704101605.1318280-1-sudeep.holla@arm.com/ > [2] https://lore.kernel.org/all/20220720-arch_topo_fixes-v3-0-43d696288e84@arm.com/ > [3] https://lore.kernel.org/all/20221107155825.1644604-1-pierre.gondois@arm.com/ > [4] On an Ampere Altra, with PREEMPT_RT kernel based on v6.0.0-rc4: > > > [ 7.560791] BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46 > [ 7.560794] in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/111 > [ 7.560796] preempt_count: 1, expected: 0 > [ 7.560797] RCU nest depth: 1, expected: 1 > [ 7.560799] 3 locks held by swapper/111/0: > [ 7.560800] #0: ffff403e406cae98 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x218/0x12c8 > [ 7.560811] #1: ffffc5f8ed09f8e8 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x48/0xf0 > [ 7.560820] #2: ffff403f400b4fd8 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x64/0xa80 > [ 7.560824] irq event stamp: 0 > [ 7.560825] hardirqs last enabled at (0): [<0000000000000000>] 0x0 > [ 7.560827] hardirqs last disabled at (0): [] copy_process+0x5dc/0x1ab8 > [ 7.560830] softirqs last enabled at (0): [] copy_process+0x5dc/0x1ab8 > [ 7.560833] softirqs last disabled at (0): [<0000000000000000>] 0x0 > [ 7.560834] Preemption disabled at: > [ 7.560835] [] migrate_enable+0x30/0x130 > [ 7.560838] CPU: 111 PID: 0 Comm: swapper/111 Tainted: G W 6.0.0-rc4-[...] > [ 7.560841] Call trace: > [...] > [ 7.560870] __kmalloc+0xbc/0x1e8 > [ 7.560873] detect_cache_attributes+0x2d4/0x5f0 > [ 7.560876] update_siblings_masks+0x30/0x368 > [ 7.560880] store_cpu_topology+0x78/0xb8 > [ 7.560883] secondary_start_kernel+0xd0/0x198 > [ 7.560885] __secondary_switched+0xb0/0xb4 > > Pierre Gondois (5): > cacheinfo: Use riscv's init_cache_level() as generic OF implem > cacheinfo: Return error code in init_of_cache_level() > ACPI: PPTT: Remove acpi_find_cache_levels() > ACPI: PPTT: Update acpi_find_last_cache_level() to > acpi_get_cache_info() > arch_topology: Build cacheinfo from primary CPU > > arch/arm64/kernel/cacheinfo.c | 9 ++- > arch/riscv/kernel/cacheinfo.c | 39 +------------ > drivers/acpi/pptt.c | 86 +++++++++++++++++------------ > drivers/base/arch_topology.c | 10 +++- > drivers/base/cacheinfo.c | 101 ++++++++++++++++++++++++++++++---- > include/linux/cacheinfo.h | 10 +++- > 6 files changed, 164 insertions(+), 91 deletions(-) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel