From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/2] Add MT8173 MMPLL change rate support
Date: Wed, 08 Jul 2015 17:44:31 -0700 [thread overview]
Message-ID: <559DC3EF.90401@codeaurora.org> (raw)
In-Reply-To: <1436344666-25645-1-git-send-email-jamesjj.liao@mediatek.com>
On 07/08/2015 01:37 AM, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
>
> James Liao (2):
> clk: mediatek: Fix PLL registers setting flow
> clk: mediatek: Add MT8173 MMPLL change rate support
>
Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
it's not clear and makes me want to defer these until v4.3. Furthermore,
the subject starts with "Add" so it sounds like a new feature.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-07-09 0:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-08 8:37 [PATCH 0/2] Add MT8173 MMPLL change rate support James Liao
2015-07-08 8:37 ` [PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow James Liao
2015-07-08 8:58 ` Heiko Stübner
2015-07-08 8:37 ` [PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support James Liao
2015-07-09 0:46 ` Stephen Boyd
2015-07-10 5:46 ` James Liao
2015-07-08 8:49 ` [PATCH 0/2] " James Liao
2015-07-09 0:44 ` Stephen Boyd [this message]
2015-07-10 5:44 ` James Liao
2015-07-14 22:13 ` Stephen Boyd
2015-07-15 9:51 ` James Liao
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