From mboxrd@z Thu Jan 1 00:00:00 1970 From: majun258@huawei.com (majun (F)) Date: Thu, 16 Jul 2015 16:35:10 +0800 Subject: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller In-Reply-To: <559D3EB5.4060408@arm.com> References: <1436166548-34920-1-git-send-email-majun258@huawei.com> <1436166548-34920-2-git-send-email-majun258@huawei.com> <559CA530.2090508@huawei.com> <559D3EB5.4060408@arm.com> Message-ID: <55A76CBE.2030508@huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org ? 2015/7/8 23:16, Marc Zyngier ??: > On 08/07/15 05:21, majun (F) wrote: >> Hi Thomas: >> [...] >>>> + >>>> + nid = GET_NODE_NUM(d->hwirq); >>>> + ret = get_mbigen_node_type(nid); >>>> + if (ret) >>>> + return 0; >>> >>> Care to explain what this does? It seems for some nodes you cannot >>> write the msi message. So how is that supposed to work? How is that >>> interrupt controlled (mask/unmask ...) ? >>> >> This function is used to write irq event id into vector register.Depends on >> hardware design, write operation is permitted in some mbigen node(nid=0,5,and >7), >> For other mbigen node, this register is read only. > > So how do you expect this to work? You cannot program the event > generated by the mbigen, and the ITS has an ITT that probably doesn't > match your HW. > > Best case, the interrupt is simply dropped, worse case you end up in an > interrupt storm because you can't figure out which device is screaming. > > I'm a bit puzzled. For interrupts connect to mbigen , the interrupt trigger type, device id and event id value are encoded in mbigen chip already. There are two types of mbigen node within a mbigen chip. Type1: event id valud can't be programmed. Type2: event id value can be programmed. For example: An device with 5 interrupts connected to Mbigen node type 1.The default event id vlaue encoded in mbigen chip for these 5 interrupt is from 0 to 4. Because the event id value can't be programmed, we need to define all of 5 interrupts in dts file so that these 5 interrupt has