From: santosh.shilimkar@oracle.com (santosh shilimkar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
Date: Fri, 31 Jul 2015 08:30:03 -0700 [thread overview]
Message-ID: <55BB947B.7090608@oracle.com> (raw)
In-Reply-To: <1432915453-409-2-git-send-email-m-karicheri2@ti.com>
Olof,
As discussed patch 1/2 is already made it via clock tree. Please
pick the subject fix for your upcoming fixes pull request.
On 5/29/2015 9:04 AM, Murali Karicheri wrote:
> All of the keystone devices have a separate register to hold post
> divider value for main pll clock. Currently the fixed-postdiv
> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
> use a value of 2 for this. Now that we have fixed this in the pll
> clock driver change the dt bindings for the same.
>
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> ---
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
next prev parent reply other threads:[~2015-07-31 15:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-29 16:04 [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
2015-05-29 16:04 ` [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll Murali Karicheri
2015-07-31 14:20 ` Murali Karicheri
2015-07-31 15:30 ` santosh shilimkar
2015-07-31 15:30 ` santosh shilimkar [this message]
2015-07-31 20:30 ` Olof Johansson
2015-07-31 22:06 ` santosh.shilimkar at oracle.com
2015-06-09 15:25 ` [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
2015-06-09 15:28 ` Fwd: " Murali Karicheri
2015-06-09 17:34 ` santosh shilimkar
2015-06-15 16:26 ` Murali Karicheri
2015-06-18 22:37 ` Michael Turquette
2015-06-18 22:55 ` santosh shilimkar
2015-06-22 20:15 ` Murali Karicheri
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