* [PATCH] thermal: rockhip: fix setting thermal shutdown polarity
@ 2015-08-07 21:00 Dmitry Torokhov
2015-08-10 6:34 ` Caesar Wang
0 siblings, 1 reply; 3+ messages in thread
From: Dmitry Torokhov @ 2015-08-07 21:00 UTC (permalink / raw)
To: linux-arm-kernel
When requested thermal shutdown signal polarity is low we need to make
sure that the bit representing high level of signal is reset, and not
set all other bits in that register.
Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better
reflect its nature.
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
---
drivers/thermal/rockchip_thermal.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index 93ee307..4d5b7d4 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -106,16 +106,14 @@ struct rockchip_thermal_data {
#define TSADCV2_AUTO_PERIOD_HT 0x6c
#define TSADCV2_AUTO_EN BIT(0)
-#define TSADCV2_AUTO_DISABLE ~BIT(0)
#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
-#define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
-#define TSADCV2_INT_PD_CLEAR ~BIT(8)
+#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
@@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs,
enum tshut_polarity tshut_polarity)
{
if (tshut_polarity == TSHUT_HIGH_ACTIVE)
- writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
+ writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
regs + TSADCV2_AUTO_CON);
else
- writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
+ writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
regs + TSADCV2_AUTO_CON);
writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
@@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs)
u32 val;
val = readl_relaxed(regs + TSADCV2_INT_PD);
- writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
+ writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
}
static void rk_tsadcv2_control(void __iomem *regs, bool enable)
--
2.5.0.rc2.392.g76e840b
--
Dmitry
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH] thermal: rockhip: fix setting thermal shutdown polarity
2015-08-07 21:00 [PATCH] thermal: rockhip: fix setting thermal shutdown polarity Dmitry Torokhov
@ 2015-08-10 6:34 ` Caesar Wang
2015-08-10 6:37 ` Caesar Wang
0 siblings, 1 reply; 3+ messages in thread
From: Caesar Wang @ 2015-08-10 6:34 UTC (permalink / raw)
To: linux-arm-kernel
Dear Dmitry,
Thanks to work for it.
? 2015?08?08? 05:00, Dmitry Torokhov ??:
> When requested thermal shutdown signal polarity is low we need to make
> sure that the bit representing high level of signal is reset, and not
> set all other bits in that register.
>
> Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better
> reflect its nature.
>
> Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Acked-by: Caesar Wang <wxt@rock-chips.com>
--
Thanks,
Caesar
> ---
> drivers/thermal/rockchip_thermal.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
> index 93ee307..4d5b7d4 100644
> --- a/drivers/thermal/rockchip_thermal.c
> +++ b/drivers/thermal/rockchip_thermal.c
> @@ -106,16 +106,14 @@ struct rockchip_thermal_data {
> #define TSADCV2_AUTO_PERIOD_HT 0x6c
>
> #define TSADCV2_AUTO_EN BIT(0)
> -#define TSADCV2_AUTO_DISABLE ~BIT(0)
> #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
> #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
> -#define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8)
>
> #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
> #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
> #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
>
> -#define TSADCV2_INT_PD_CLEAR ~BIT(8)
> +#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
>
> #define TSADCV2_DATA_MASK 0xfff
> #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
> @@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs,
> enum tshut_polarity tshut_polarity)
> {
> if (tshut_polarity == TSHUT_HIGH_ACTIVE)
> - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
> + writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
> regs + TSADCV2_AUTO_CON);
> else
> - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
> + writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
> regs + TSADCV2_AUTO_CON);
>
> writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
> @@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs)
> u32 val;
>
> val = readl_relaxed(regs + TSADCV2_INT_PD);
> - writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
> + writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
> }
>
> static void rk_tsadcv2_control(void __iomem *regs, bool enable)
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH] thermal: rockhip: fix setting thermal shutdown polarity
2015-08-10 6:34 ` Caesar Wang
@ 2015-08-10 6:37 ` Caesar Wang
0 siblings, 0 replies; 3+ messages in thread
From: Caesar Wang @ 2015-08-10 6:37 UTC (permalink / raw)
To: linux-arm-kernel
Sorry, forgot it!
\s 'rockhip' to 'rockchip' :-)
? 2015?08?10? 14:34, Caesar Wang ??:
> Dear Dmitry,
>
> Thanks to work for it.
>
> ? 2015?08?08? 05:00, Dmitry Torokhov ??:
>> When requested thermal shutdown signal polarity is low we need to make
>> sure that the bit representing high level of signal is reset, and not
>> set all other bits in that register.
>>
>> Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better
>> reflect its nature.
>>
>> Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
>
> Acked-by: Caesar Wang <wxt@rock-chips.com>
>
> --
> Thanks,
> Caesar
>
>> ---
>> drivers/thermal/rockchip_thermal.c | 10 ++++------
>> 1 file changed, 4 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/thermal/rockchip_thermal.c
>> b/drivers/thermal/rockchip_thermal.c
>> index 93ee307..4d5b7d4 100644
>> --- a/drivers/thermal/rockchip_thermal.c
>> +++ b/drivers/thermal/rockchip_thermal.c
>> @@ -106,16 +106,14 @@ struct rockchip_thermal_data {
>> #define TSADCV2_AUTO_PERIOD_HT 0x6c
>> #define TSADCV2_AUTO_EN BIT(0)
>> -#define TSADCV2_AUTO_DISABLE ~BIT(0)
>> #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
>> #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
>> -#define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8)
>> #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
>> #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
>> #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
>> -#define TSADCV2_INT_PD_CLEAR ~BIT(8)
>> +#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
>> #define TSADCV2_DATA_MASK 0xfff
>> #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
>> @@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem
>> *regs,
>> enum tshut_polarity tshut_polarity)
>> {
>> if (tshut_polarity == TSHUT_HIGH_ACTIVE)
>> - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH),
>> + writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
>> regs + TSADCV2_AUTO_CON);
>> else
>> - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW),
>> + writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
>> regs + TSADCV2_AUTO_CON);
>> writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs +
>> TSADCV2_AUTO_PERIOD);
>> @@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs)
>> u32 val;
>> val = readl_relaxed(regs + TSADCV2_INT_PD);
>> - writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD);
>> + writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs +
>> TSADCV2_INT_PD);
>> }
>> static void rk_tsadcv2_control(void __iomem *regs, bool enable)
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-08-10 6:37 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-08-07 21:00 [PATCH] thermal: rockhip: fix setting thermal shutdown polarity Dmitry Torokhov
2015-08-10 6:34 ` Caesar Wang
2015-08-10 6:37 ` Caesar Wang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).