[PATCH 0/5] Host1x/TegraDRM fixes/improvements

[PATCH 0/5] Host1x/TegraDRM fixes/improvements

[Mikko Perttunen]

Hi, this series has a few small improvements for Host1x and TegraDRM
that the VIC series will build upon.

1/5 is a bug fix to host1x.
2/5 is required by VIC code to implement ->is_addr_reg().
3/5 deduplicates handling of HOST1X class address registers
    and fixes the checked registers.
4/5 is required for the host1x firewall to work when bo's are
    mapped using IOMMU.
5/5 adds a TegraDRM allocator that allows drivers to allocate
    non-GEM memory that is still mapped to the TegraDRM domain.

Arto Merilainen (3):
  host1x: Store device address to all bufs
  host1x: Pass register value in firewall
  drm/tegra: Support kernel mappings with IOMMU

Mikko Perttunen (2):
  host1x: Handle HOST1X class address registers directly
  drm/tegra: Add Tegra DRM allocation API

 drivers/gpu/drm/tegra/drm.c  | 99 +++++++++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/tegra/drm.h  | 13 +++++-
 drivers/gpu/drm/tegra/gem.c  | 34 +++++++++++++--
 drivers/gpu/drm/tegra/gr2d.c | 25 ++++-------
 drivers/gpu/drm/tegra/gr3d.c | 24 ++++-------
 drivers/gpu/host1x/job.c     | 54 +++++++++++++++++-------
 include/linux/host1x.h       |  4 +-
 7 files changed, 193 insertions(+), 60 deletions(-)

-- 
2.1.4

[PATCH 1/5] host1x: Store device address to all bufs

[Mikko Perttunen]

From: Arto Merilainen <amerilainen@nvidia.com>

Currently job pinning is optimized to handle only the first buffer
using a certain host1x_bo object and all subsequent buffers using
the same host1x_bo are considered done.

In most cases this is correct, however, in case the same host1x_bo
is used in multiple gathers inside the same job, we skip also
storing the device address (physical or iova) to this buffer.

This patch reworks the host1x_job_pin() to store the device address
to all gathers.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/job.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index 63bd63f..b72aa91 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -1,7 +1,7 @@
 /*
  * Tegra host1x Job
  *
- * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2010-2015, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -538,9 +538,12 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev)
 
 		g->base = job->gather_addr_phys[i];
 
-		for (j = i + 1; j < job->num_gathers; j++)
-			if (job->gathers[j].bo == g->bo)
+		for (j = i + 1; j < job->num_gathers; j++) {
+			if (job->gathers[j].bo == g->bo) {
 				job->gathers[j].handled = true;
+				job->gathers[j].base = g->base;
+			}
+		}
 
 		err = do_relocs(job, g->bo);
 		if (err)
-- 
2.1.4

[PATCH 2/5] host1x: Pass register value in firewall

[Mikko Perttunen]

From: Arto Merilainen <amerilainen@nvidia.com>

In gr2d and gr3d units the register offset was sufficient for determining
if the register in interest is used for storing a register value.

However, in VIC this is not the case. The operations are passed through
two registers, METHOD0 and METHOD1. Depending on content of METHOD0,
METHOD1 can be either address or data field.

This patch updates the firewall interface to deliver also the register
value to allow book-keeping inside the engine driver.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/drm/tegra/drm.h  |  4 ++--
 drivers/gpu/drm/tegra/gr2d.c |  4 ++--
 drivers/gpu/drm/tegra/gr3d.c |  4 ++--
 drivers/gpu/host1x/job.c     | 35 +++++++++++++++++++++++------------
 include/linux/host1x.h       |  4 ++--
 5 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 659b2fc..0e7756e 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2012 Avionic Design GmbH
- * Copyright (C) 2012-2013 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2012-2015 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -70,7 +70,7 @@ struct tegra_drm_client_ops {
 	int (*open_channel)(struct tegra_drm_client *client,
 			    struct tegra_drm_context *context);
 	void (*close_channel)(struct tegra_drm_context *context);
-	int (*is_addr_reg)(struct device *dev, u32 class, u32 offset);
+	int (*is_addr_reg)(struct device *dev, u32 class, u32 offset, u32 val);
 	int (*submit)(struct tegra_drm_context *context,
 		      struct drm_tegra_submit *args, struct drm_device *drm,
 		      struct drm_file *file);
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 02cd3e3..7e4424f 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA Corporation.
+ * Copyright (c) 2012-2015, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -84,7 +84,7 @@ static void gr2d_close_channel(struct tegra_drm_context *context)
 	host1x_channel_put(context->channel);
 }
 
-static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset)
+static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset, u32 val)
 {
 	struct gr2d *gr2d = dev_get_drvdata(dev);
 
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 0b3f2b9..9ceaf35 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2013 Avionic Design GmbH
- * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (C) 2013-2015 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -94,7 +94,7 @@ static void gr3d_close_channel(struct tegra_drm_context *context)
 	host1x_channel_put(context->channel);
 }
 
-static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
+static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset, u32 val)
 {
 	struct gr3d *gr3d = dev_get_drvdata(dev);
 
diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index b72aa91..77d977b 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -295,9 +295,10 @@ struct host1x_firewall {
 	u32 count;
 };
 
-static int check_register(struct host1x_firewall *fw, unsigned long offset)
+static int check_register(struct host1x_firewall *fw,
+			  unsigned long offset, u32 val)
 {
-	if (fw->job->is_addr_reg(fw->dev, fw->class, offset)) {
+	if (fw->job->is_addr_reg(fw->dev, fw->class, offset, val)) {
 		if (!fw->num_relocs)
 			return -EINVAL;
 
@@ -311,18 +312,21 @@ static int check_register(struct host1x_firewall *fw, unsigned long offset)
 	return 0;
 }
 
-static int check_mask(struct host1x_firewall *fw)
+static int check_mask(struct host1x_firewall *fw, struct host1x_job_gather *g)
 {
+	u32 *cmdbuf_base = (u32 *)fw->job->gather_copy_mapped +
+		(g->offset / sizeof(u32));
 	u32 mask = fw->mask;
 	u32 reg = fw->reg;
 	int ret;
 
 	while (mask) {
+		u32 val = cmdbuf_base[fw->offset];
 		if (fw->words == 0)
 			return -EINVAL;
 
 		if (mask & 1) {
-			ret = check_register(fw, reg);
+			ret = check_register(fw, reg, val);
 			if (ret < 0)
 				return ret;
 
@@ -336,17 +340,20 @@ static int check_mask(struct host1x_firewall *fw)
 	return 0;
 }
 
-static int check_incr(struct host1x_firewall *fw)
+static int check_incr(struct host1x_firewall *fw, struct host1x_job_gather *g)
 {
+	u32 *cmdbuf_base = (u32 *)fw->job->gather_copy_mapped +
+		(g->offset / sizeof(u32));
 	u32 count = fw->count;
 	u32 reg = fw->reg;
 	int ret;
 
 	while (count) {
+		u32 val = cmdbuf_base[fw->offset];
 		if (fw->words == 0)
 			return -EINVAL;
 
-		ret = check_register(fw, reg);
+		ret = check_register(fw, reg, val);
 		if (ret < 0)
 			return ret;
 
@@ -359,16 +366,20 @@ static int check_incr(struct host1x_firewall *fw)
 	return 0;
 }
 
-static int check_nonincr(struct host1x_firewall *fw)
+static int check_nonincr(struct host1x_firewall *fw,
+			 struct host1x_job_gather *g)
 {
+	u32 *cmdbuf_base = (u32 *)fw->job->gather_copy_mapped +
+		(g->offset / sizeof(u32));
 	u32 count = fw->count;
 	int ret;
 
 	while (count) {
+		u32 val = cmdbuf_base[fw->offset];
 		if (fw->words == 0)
 			return -EINVAL;
 
-		ret = check_register(fw, fw->reg);
+		ret = check_register(fw, fw->reg, val);
 		if (ret < 0)
 			return ret;
 
@@ -408,14 +419,14 @@ static int validate(struct host1x_firewall *fw, struct host1x_job_gather *g)
 			fw->class = word >> 6 & 0x3ff;
 			fw->mask = word & 0x3f;
 			fw->reg = word >> 16 & 0xfff;
-			err = check_mask(fw);
+			err = check_mask(fw, g);
 			if (err)
 				goto out;
 			break;
 		case 1:
 			fw->reg = word >> 16 & 0xfff;
 			fw->count = word & 0xffff;
-			err = check_incr(fw);
+			err = check_incr(fw, g);
 			if (err)
 				goto out;
 			break;
@@ -423,7 +434,7 @@ static int validate(struct host1x_firewall *fw, struct host1x_job_gather *g)
 		case 2:
 			fw->reg = word >> 16 & 0xfff;
 			fw->count = word & 0xffff;
-			err = check_nonincr(fw);
+			err = check_nonincr(fw, g);
 			if (err)
 				goto out;
 			break;
@@ -431,7 +442,7 @@ static int validate(struct host1x_firewall *fw, struct host1x_job_gather *g)
 		case 3:
 			fw->mask = word & 0xffff;
 			fw->reg = word >> 16 & 0xfff;
-			err = check_mask(fw);
+			err = check_mask(fw, g);
 			if (err)
 				goto out;
 			break;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index d2ba7d3..fc86ced 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2013, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2009-2015, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -225,7 +225,7 @@ struct host1x_job {
 	u8 *gather_copy_mapped;
 
 	/* Check if register is marked as an address reg */
-	int (*is_addr_reg)(struct device *dev, u32 reg, u32 class);
+	int (*is_addr_reg)(struct device *dev, u32 reg, u32 class, u32 val);
 
 	/* Request a SETCLASS to this class */
 	u32 class;
-- 
2.1.4

[PATCH 3/5] host1x: Handle HOST1X class address registers directly

[Mikko Perttunen]

This moves handling of address registers in the HOST1X class directly
to the firewall code in host1x's job.c, so that individual clients don't
have to replicate this code. The list of address registers detected also
change from INDCTRL which is not actually an address register to INDOFF
and INDOFF2 which are.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/drm/tegra/gr2d.c | 21 ++++++---------------
 drivers/gpu/drm/tegra/gr3d.c | 20 ++++++--------------
 drivers/gpu/host1x/job.c     | 12 +++++++++++-
 3 files changed, 23 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 7e4424f..f048d45 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -88,23 +88,14 @@ static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset, u32 val)
 {
 	struct gr2d *gr2d = dev_get_drvdata(dev);
 
-	switch (class) {
-	case HOST1X_CLASS_HOST1X:
-		if (offset == 0x2b)
-			return 1;
+	if (class != HOST1X_CLASS_GR2D && class != HOST1X_CLASS_GR2D_SB)
+		return 0;
 
-		break;
+	if (offset >= GR2D_NUM_REGS)
+		return 0;
 
-	case HOST1X_CLASS_GR2D:
-	case HOST1X_CLASS_GR2D_SB:
-		if (offset >= GR2D_NUM_REGS)
-			break;
-
-		if (test_bit(offset, gr2d->addr_regs))
-			return 1;
-
-		break;
-	}
+	if (test_bit(offset, gr2d->addr_regs))
+		return 1;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 9ceaf35..d0dab15 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -98,22 +98,14 @@ static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset, u32 val)
 {
 	struct gr3d *gr3d = dev_get_drvdata(dev);
 
-	switch (class) {
-	case HOST1X_CLASS_HOST1X:
-		if (offset == 0x2b)
-			return 1;
+	if (class != HOST1X_CLASS_GR3D)
+		return 0;
 
-		break;
+	if (offset >= GR3D_NUM_REGS)
+		return 0;
 
-	case HOST1X_CLASS_GR3D:
-		if (offset >= GR3D_NUM_REGS)
-			break;
-
-		if (test_bit(offset, gr3d->addr_regs))
-			return 1;
-
-		break;
-	}
+	if (test_bit(offset, gr3d->addr_regs))
+		return 1;
 
 	return 0;
 }
diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index 77d977b..0701008 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -295,10 +295,20 @@ struct host1x_firewall {
 	u32 count;
 };
 
+static int is_addr_reg(struct host1x_firewall *fw, unsigned long offset,
+		       u32 val)
+{
+	if (fw->class == HOST1X_CLASS_HOST1X &&
+		(offset == 0x2c /* INDOFF2 */ || offset == 0x2d /* INDOFF */))
+		return true;
+
+	return fw->job->is_addr_reg(fw->dev, fw->class, offset, val);
+}
+
 static int check_register(struct host1x_firewall *fw,
 			  unsigned long offset, u32 val)
 {
-	if (fw->job->is_addr_reg(fw->dev, fw->class, offset, val)) {
+	if (is_addr_reg(fw, offset, val)) {
 		if (!fw->num_relocs)
 			return -EINVAL;
 
-- 
2.1.4

[PATCH 4/5] drm/tegra: Support kernel mappings with IOMMU

[Mikko Perttunen]

From: Arto Merilainen <amerilainen@nvidia.com>

Host1x command buffer patching requires that the buffer object can be
mapped into kernel address space, however, the recent addition of
IOMMU did not account to this requirement. Therefore Host1x engines
cannot be used if IOMMU is enabled.

This patch implements kmap, kunmap, mmap and munmap functions to
host1x bo objects.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/drm/tegra/gem.c | 34 +++++++++++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index 01e16e1..6aed866 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -2,7 +2,7 @@
  * NVIDIA Tegra DRM GEM helper functions
  *
  * Copyright (C) 2012 Sascha Hauer, Pengutronix
- * Copyright (C) 2013 NVIDIA CORPORATION, All rights reserved.
+ * Copyright (C) 2013-2015 NVIDIA CORPORATION, All rights reserved.
  *
  * Based on the GEM/CMA helpers
  *
@@ -50,23 +50,51 @@ static void *tegra_bo_mmap(struct host1x_bo *bo)
 {
 	struct tegra_bo *obj = host1x_to_tegra_bo(bo);
 
-	return obj->vaddr;
+	if (obj->vaddr)
+		return obj->vaddr;
+	else if (obj->gem.import_attach)
+		return dma_buf_vmap(obj->gem.import_attach->dmabuf);
+	else
+		return vmap(obj->pages, obj->num_pages, VM_MAP,
+			    pgprot_writecombine(PAGE_KERNEL));
 }
 
 static void tegra_bo_munmap(struct host1x_bo *bo, void *addr)
 {
+	struct tegra_bo *obj = host1x_to_tegra_bo(bo);
+
+	if (obj->vaddr)
+		return;
+	else if (obj->gem.import_attach)
+		dma_buf_vunmap(obj->gem.import_attach->dmabuf, addr);
+	else
+		vunmap(addr);
 }
 
 static void *tegra_bo_kmap(struct host1x_bo *bo, unsigned int page)
 {
 	struct tegra_bo *obj = host1x_to_tegra_bo(bo);
 
-	return obj->vaddr + page * PAGE_SIZE;
+	if (obj->vaddr)
+		return obj->vaddr + page * PAGE_SIZE;
+	else if (obj->gem.import_attach)
+		return dma_buf_kmap(obj->gem.import_attach->dmabuf, page);
+	else
+		return vmap(obj->pages + page, 1, VM_MAP,
+			    pgprot_writecombine(PAGE_KERNEL));
 }
 
 static void tegra_bo_kunmap(struct host1x_bo *bo, unsigned int page,
 			    void *addr)
 {
+	struct tegra_bo *obj = host1x_to_tegra_bo(bo);
+
+	if (obj->vaddr)
+		return;
+	else if (obj->gem.import_attach)
+		dma_buf_kunmap(obj->gem.import_attach->dmabuf, page, addr);
+	else
+		vunmap(addr);
 }
 
 static struct host1x_bo *tegra_bo_get(struct host1x_bo *bo)
-- 
2.1.4

[PATCH 5/5] drm/tegra: Add Tegra DRM allocation API

[Mikko Perttunen]

Add a new IO virtual memory allocation API to allow clients to
allocate non-GEM memory in the Tegra DRM IOMMU domain. This is
required e.g. for loading client firmware when clients are attached
to the IOMMU domain.

The allocator allocates contiguous physical pages that are then
mapped contiguously to the IOMMU domain using a bitmap allocator
inside a 64 MiB reserved for non-GEM allocations. Contiguous
physical pages are used so that the same allocator works also
when IOMMU support is disabled and therefore devices access
physical memory directly.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/drm/tegra/drm.c | 99 ++++++++++++++++++++++++++++++++++++++++++---
 drivers/gpu/drm/tegra/drm.h |  9 +++++
 2 files changed, 103 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 427f50c..af4ff86 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1,12 +1,13 @@
 /*
  * Copyright (C) 2012 Avionic Design GmbH
- * Copyright (C) 2012-2013 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2012-2015 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
+#include <linux/bitops.h>
 #include <linux/host1x.h>
 #include <linux/iommu.h>
 
@@ -23,6 +24,8 @@
 #define DRIVER_MINOR 0
 #define DRIVER_PATCHLEVEL 0
 
+#define IOVA_AREA_SZ (1024 * 1024 * 64) /* 64 MiB */
+
 struct tegra_drm_file {
 	struct list_head contexts;
 };
@@ -125,7 +128,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
 
 	if (iommu_present(&platform_bus_type)) {
 		struct iommu_domain_geometry *geometry;
-		u64 start, end;
+		u64 start, end, iova_start;
+		size_t bitmap_size;
 
 		tegra->domain = iommu_domain_alloc(&platform_bus_type);
 		if (!tegra->domain) {
@@ -136,10 +140,23 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
 		geometry = &tegra->domain->geometry;
 		start = geometry->aperture_start;
 		end = geometry->aperture_end;
+		iova_start = end - IOVA_AREA_SZ + 1;
+
+		DRM_DEBUG("IOMMU context initialized (GEM aperture: %#llx-%#llx, IOVA aperture: %#llx-%#llx)\n",
+			  start, iova_start-1, iova_start, end);
+		bitmap_size = BITS_TO_LONGS(IOVA_AREA_SZ >> PAGE_SHIFT) *
+			sizeof(long);
+		tegra->iova_bitmap = devm_kzalloc(drm->dev, bitmap_size,
+						  GFP_KERNEL);
+		if (!tegra->iova_bitmap) {
+			err = -ENOMEM;
+			goto free;
+		}
+		tegra->iova_bitmap_bits = BITS_PER_BYTE * bitmap_size;
+		tegra->iova_start = iova_start;
+		mutex_init(&tegra->iova_lock);
 
-		DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n",
-			  start, end);
-		drm_mm_init(&tegra->mm, start, end - start + 1);
+		drm_mm_init(&tegra->mm, start, iova_start - start);
 	}
 
 	mutex_init(&tegra->clients_lock);
@@ -979,6 +996,78 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra,
 	return 0;
 }
 
+void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
+			      dma_addr_t *iova)
+{
+	size_t aligned = PAGE_ALIGN(size);
+	int num_pages = aligned >> PAGE_SHIFT;
+	void *virt;
+	unsigned int start;
+	int err;
+
+	virt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
+					get_order(aligned));
+	if (!virt)
+		return NULL;
+
+	if (!tegra->domain) {
+		/*
+		 * If IOMMU is disabled, devices address physical memory
+		 * directly.
+		 */
+		*iova = virt_to_phys(virt);
+		return virt;
+	}
+
+	mutex_lock(&tegra->iova_lock);
+
+	start = bitmap_find_next_zero_area(tegra->iova_bitmap,
+					   tegra->iova_bitmap_bits, 0,
+					   num_pages, 0);
+	if (start > tegra->iova_bitmap_bits)
+		goto free_pages;
+
+	bitmap_set(tegra->iova_bitmap, start, num_pages);
+
+	*iova = tegra->iova_start + (start << PAGE_SHIFT);
+	err = iommu_map(tegra->domain, *iova, virt_to_phys(virt),
+			aligned, IOMMU_READ | IOMMU_WRITE);
+	if (err < 0)
+		goto free_iova;
+
+	mutex_unlock(&tegra->iova_lock);
+
+	return virt;
+
+free_iova:
+	bitmap_clear(tegra->iova_bitmap, start, num_pages);
+free_pages:
+	mutex_unlock(&tegra->iova_lock);
+
+	free_pages((unsigned long)virt, get_order(aligned));
+
+	return NULL;
+}
+
+void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
+		    dma_addr_t iova)
+{
+	size_t aligned = PAGE_ALIGN(size);
+	int num_pages = aligned >> PAGE_SHIFT;
+
+	if (tegra->domain) {
+		unsigned int start = (iova - tegra->iova_start) >> PAGE_SHIFT;
+
+		iommu_unmap(tegra->domain, iova, aligned);
+
+		mutex_lock(&tegra->iova_lock);
+		bitmap_clear(tegra->iova_bitmap, start, num_pages);
+		mutex_unlock(&tegra->iova_lock);
+	}
+
+	free_pages((unsigned long)virt, get_order(aligned));
+}
+
 static int host1x_drm_probe(struct host1x_device *dev)
 {
 	struct drm_driver *driver = &tegra_drm_driver;
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 0e7756e..58c83b11 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -42,6 +42,11 @@ struct tegra_drm {
 	struct iommu_domain *domain;
 	struct drm_mm mm;
 
+	struct mutex iova_lock;
+	dma_addr_t iova_start;
+	unsigned long *iova_bitmap;
+	unsigned int iova_bitmap_bits;
+
 	struct mutex clients_lock;
 	struct list_head clients;
 
@@ -101,6 +106,10 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra,
 int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm);
 int tegra_drm_exit(struct tegra_drm *tegra);
 
+void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *iova);
+void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
+		    dma_addr_t iova);
+
 struct tegra_dc_soc_info;
 struct tegra_output;
 
-- 
2.1.4

[PATCH 0/5] Host1x/TegraDRM fixes/improvements

[Mikko Perttunen]

Bump.

On 07/08/2015 02:27 PM, Mikko Perttunen wrote:
> Hi, this series has a few small improvements for Host1x and TegraDRM
> that the VIC series will build upon.
> 
> 1/5 is a bug fix to host1x.
> 2/5 is required by VIC code to implement ->is_addr_reg().
> 3/5 deduplicates handling of HOST1X class address registers
>     and fixes the checked registers.
> 4/5 is required for the host1x firewall to work when bo's are
>     mapped using IOMMU.
> 5/5 adds a TegraDRM allocator that allows drivers to allocate
>     non-GEM memory that is still mapped to the TegraDRM domain.
> 
> Arto Merilainen (3):
>   host1x: Store device address to all bufs
>   host1x: Pass register value in firewall
>   drm/tegra: Support kernel mappings with IOMMU
> 
> Mikko Perttunen (2):
>   host1x: Handle HOST1X class address registers directly
>   drm/tegra: Add Tegra DRM allocation API
> 
>  drivers/gpu/drm/tegra/drm.c  | 99 +++++++++++++++++++++++++++++++++++++++++---
>  drivers/gpu/drm/tegra/drm.h  | 13 +++++-
>  drivers/gpu/drm/tegra/gem.c  | 34 +++++++++++++--
>  drivers/gpu/drm/tegra/gr2d.c | 25 ++++-------
>  drivers/gpu/drm/tegra/gr3d.c | 24 ++++-------
>  drivers/gpu/host1x/job.c     | 54 +++++++++++++++++-------
>  include/linux/host1x.h       |  4 +-
>  7 files changed, 193 insertions(+), 60 deletions(-)
>