* [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks
@ 2015-08-11 3:46 Chanwoo Choi
2015-08-11 3:46 ` [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Chanwoo Choi @ 2015-08-11 3:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch add the UART2 / MMC2 devicetree node for Exynos3250 SoC and add
the related clocks (mux, divider, gate) of UART2 / MMC2 device.
Chanwoo Choi (4):
clk: samsung: exynos3250: Add UART2 clock
clk: samsung: exynos3250: Add MMC2 clock
ARM: dts: Add UART2 dt node for Exynos3250 SoC
ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 42 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 25 ++++++++++++++++++
drivers/clk/samsung/clk-exynos3250.c | 15 +++++++++++
include/dt-bindings/clock/exynos3250.h | 11 +++++++-
4 files changed, 92 insertions(+), 1 deletion(-)
--
1.8.5.5
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock
2015-08-11 3:46 [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Chanwoo Choi
@ 2015-08-11 3:46 ` Chanwoo Choi
2015-08-17 1:01 ` Krzysztof Kozlowski
2015-08-17 3:29 ` [1/4] " Pankaj Dubey
2015-08-11 3:46 ` [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
` (3 subsequent siblings)
4 siblings, 2 replies; 14+ messages in thread
From: Chanwoo Choi @ 2015-08-11 3:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clk/samsung/clk-exynos3250.c | 6 ++++++
include/dt-bindings/clock/exynos3250.h | 6 +++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 538de66a759e..2105863a3ace 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -307,6 +307,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
/* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -389,6 +390,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_PERIL0 */
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -551,6 +553,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -648,6 +653,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index aab088d30199..89a7d97b002c 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -78,6 +78,7 @@
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
+#define CLK_MOUT_UART2 61
/* Dividers */
#define CLK_DIV_GPL 64
@@ -126,6 +127,7 @@
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
+#define CLK_DIV_UART2 110
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -222,6 +224,7 @@
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
+#define CLK_UART2 222
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -248,12 +251,13 @@
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
+#define CLK_SCLK_UART2 248
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 248
+#define CLK_NR_CLKS 249
/*
* CMU DMC
--
1.8.5.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock
2015-08-11 3:46 [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Chanwoo Choi
2015-08-11 3:46 ` [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
@ 2015-08-11 3:46 ` Chanwoo Choi
2015-08-17 1:48 ` Krzysztof Kozlowski
2015-08-11 3:46 ` [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Chanwoo Choi @ 2015-08-11 3:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++
include/dt-bindings/clock/exynos3250.h | 7 ++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 2105863a3ace..2683cf03e656 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -303,6 +303,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
/* SRC_FSYS */
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+ MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
@@ -389,6 +390,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ /* DIV_FSYS2 */
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
/* DIV_PERIL0 */
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
@@ -539,6 +545,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+ GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -634,6 +642,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index 89a7d97b002c..fbc9ef61b191 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,7 @@
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
#define CLK_MOUT_UART2 61
+#define CLK_MOUT_MMC2 62
/* Dividers */
#define CLK_DIV_GPL 64
@@ -128,6 +129,8 @@
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
#define CLK_DIV_UART2 110
+#define CLK_DIV_MMC2_PRE 111
+#define CLK_DIV_MMC2 112
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -225,6 +228,7 @@
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
#define CLK_UART2 222
+#define CLK_SDMMC2 223
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -252,12 +256,13 @@
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
#define CLK_SCLK_UART2 248
+#define CLK_SCLK_MMC2 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 249
+#define CLK_NR_CLKS 250
/*
* CMU DMC
--
1.8.5.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC
2015-08-11 3:46 [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Chanwoo Choi
2015-08-11 3:46 ` [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
2015-08-11 3:46 ` [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
@ 2015-08-11 3:46 ` Chanwoo Choi
2015-08-17 2:11 ` Krzysztof Kozlowski
2015-08-17 3:33 ` [3/4] " Pankaj Dubey
2015-08-11 3:46 ` [PATCH 4/4] ARM: dts: Add MSHC2 " Chanwoo Choi
2015-08-17 0:33 ` [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Krzysztof Kozlowski
4 siblings, 2 replies; 14+ messages in thread
From: Chanwoo Choi @ 2015-08-11 3:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch add the uart2 devicetree node for Exynos3250 SoC.
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 5ab81c39e2c9..eac1d21c10d4 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -120,6 +120,13 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 2db99433e17f..02f3250766c9 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
};
cpus {
@@ -435,6 +436,17 @@
status = "disabled";
};
+ serial_2: serial at 13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c at 13860000 {
#address-cells = <1>;
#size-cells = <0>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/4] ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
2015-08-11 3:46 [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Chanwoo Choi
` (2 preceding siblings ...)
2015-08-11 3:46 ` [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
@ 2015-08-11 3:46 ` Chanwoo Choi
2015-08-17 2:13 ` Krzysztof Kozlowski
2015-08-17 0:33 ` [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Krzysztof Kozlowski
4 siblings, 1 reply; 14+ messages in thread
From: Chanwoo Choi @ 2015-08-11 3:46 UTC (permalink / raw)
To: linux-arm-kernel
This patch add the MSHC2 (Mobile Storage Host Controller) devicetree node for
Exynos3250 SoC.
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index eac1d21c10d4..78b995fed6c7 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -452,6 +452,41 @@
samsung,pin-drv = <3>;
};
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 02f3250766c9..5a91eaa26565 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -30,6 +30,7 @@
pinctrl1 = &pinctrl_1;
mshc0 = &mshc_0;
mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
spi0 = &spi_0;
spi1 = &spi_1;
i2c0 = &i2c_0;
@@ -341,6 +342,18 @@
status = "disabled";
};
+ mshc_2: mshc at 12530000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12530000 0x1000>;
+ interrupts = <0 144 0>;
+ clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
exynos_usbphy: exynos-usbphy at 125B0000 {
compatible = "samsung,exynos3250-usb2-phy";
reg = <0x125B0000 0x100>;
--
1.8.5.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks
2015-08-11 3:46 [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Chanwoo Choi
` (3 preceding siblings ...)
2015-08-11 3:46 ` [PATCH 4/4] ARM: dts: Add MSHC2 " Chanwoo Choi
@ 2015-08-17 0:33 ` Krzysztof Kozlowski
2015-08-17 0:36 ` Chanwoo Choi
4 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2015-08-17 0:33 UTC (permalink / raw)
To: linux-arm-kernel
2015-08-11 12:46 GMT+09:00 Chanwoo Choi <cw00.choi@samsung.com>:
> This patch add the UART2 / MMC2 devicetree node for Exynos3250 SoC and add
> the related clocks (mux, divider, gate) of UART2 / MMC2 device.
What is the benefit of adding them? Why they are needed?
Best regards,
Krzysztof
>
> Chanwoo Choi (4):
> clk: samsung: exynos3250: Add UART2 clock
> clk: samsung: exynos3250: Add MMC2 clock
> ARM: dts: Add UART2 dt node for Exynos3250 SoC
> ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
>
> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 42 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos3250.dtsi | 25 ++++++++++++++++++
> drivers/clk/samsung/clk-exynos3250.c | 15 +++++++++++
> include/dt-bindings/clock/exynos3250.h | 11 +++++++-
> 4 files changed, 92 insertions(+), 1 deletion(-)
>
> --
> 1.8.5.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks
2015-08-17 0:33 ` [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Krzysztof Kozlowski
@ 2015-08-17 0:36 ` Chanwoo Choi
2015-08-17 0:37 ` Krzysztof Kozlowski
0 siblings, 1 reply; 14+ messages in thread
From: Chanwoo Choi @ 2015-08-17 0:36 UTC (permalink / raw)
To: linux-arm-kernel
On 08/17/2015 09:33 AM, Krzysztof Kozlowski wrote:
> 2015-08-11 12:46 GMT+09:00 Chanwoo Choi <cw00.choi@samsung.com>:
>> This patch add the UART2 / MMC2 devicetree node for Exynos3250 SoC and add
>> the related clocks (mux, divider, gate) of UART2 / MMC2 device.
>
> What is the benefit of adding them? Why they are needed?
UART2 /MMC2 are used on Exynos3250-based ARTIK-5 board[1].
[1] https://www.artik.io/hardware/artik-5
Thanks,
Chanwoo Choi
>
> Best regards,
> Krzysztof
>
>
>>
>> Chanwoo Choi (4):
>> clk: samsung: exynos3250: Add UART2 clock
>> clk: samsung: exynos3250: Add MMC2 clock
>> ARM: dts: Add UART2 dt node for Exynos3250 SoC
>> ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
>>
>> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 42 +++++++++++++++++++++++++++++++
>> arch/arm/boot/dts/exynos3250.dtsi | 25 ++++++++++++++++++
>> drivers/clk/samsung/clk-exynos3250.c | 15 +++++++++++
>> include/dt-bindings/clock/exynos3250.h | 11 +++++++-
>> 4 files changed, 92 insertions(+), 1 deletion(-)
>>
>> --
>> 1.8.5.5
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks
2015-08-17 0:36 ` Chanwoo Choi
@ 2015-08-17 0:37 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2015-08-17 0:37 UTC (permalink / raw)
To: linux-arm-kernel
On 17.08.2015 09:36, Chanwoo Choi wrote:
> On 08/17/2015 09:33 AM, Krzysztof Kozlowski wrote:
>> 2015-08-11 12:46 GMT+09:00 Chanwoo Choi <cw00.choi@samsung.com>:
>>> This patch add the UART2 / MMC2 devicetree node for Exynos3250 SoC and add
>>> the related clocks (mux, divider, gate) of UART2 / MMC2 device.
>>
>> What is the benefit of adding them? Why they are needed?
>
> UART2 /MMC2 are used on Exynos3250-based ARTIK-5 board[1].
> [1] https://www.artik.io/hardware/artik-5
Thanks for explaining this. The patchset missed that information - the
purpose. I'll start reviewing it.
Best regards,
Krzysztof
>
> Thanks,
> Chanwoo Choi
>
>>
>> Best regards,
>> Krzysztof
>>
>>
>>>
>>> Chanwoo Choi (4):
>>> clk: samsung: exynos3250: Add UART2 clock
>>> clk: samsung: exynos3250: Add MMC2 clock
>>> ARM: dts: Add UART2 dt node for Exynos3250 SoC
>>> ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
>>>
>>> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 42 +++++++++++++++++++++++++++++++
>>> arch/arm/boot/dts/exynos3250.dtsi | 25 ++++++++++++++++++
>>> drivers/clk/samsung/clk-exynos3250.c | 15 +++++++++++
>>> include/dt-bindings/clock/exynos3250.h | 11 +++++++-
>>> 4 files changed, 92 insertions(+), 1 deletion(-)
>>>
>>> --
>>> 1.8.5.5
>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock
2015-08-11 3:46 ` [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
@ 2015-08-17 1:01 ` Krzysztof Kozlowski
2015-08-17 3:29 ` [1/4] " Pankaj Dubey
1 sibling, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2015-08-17 1:01 UTC (permalink / raw)
To: linux-arm-kernel
On 11.08.2015 12:46, Chanwoo Choi wrote:
> This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
I could not confirm the exact numbers used ("reserved" in my datasheet)
but the patch itself looks correct.
Assuming that numbers/addresses are good:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 6 ++++++
> include/dt-bindings/clock/exynos3250.h | 6 +++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock
2015-08-11 3:46 ` [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
@ 2015-08-17 1:48 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2015-08-17 1:48 UTC (permalink / raw)
To: linux-arm-kernel
On 11.08.2015 12:46, Chanwoo Choi wrote:
> This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++
> include/dt-bindings/clock/exynos3250.h | 7 ++++++-
> 2 files changed, 15 insertions(+), 1 deletion(-)
Assuming that numbers/addresses are good (reserved in my datasheet) the
code itself looks good:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC
2015-08-11 3:46 ` [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
@ 2015-08-17 2:11 ` Krzysztof Kozlowski
2015-08-17 3:33 ` [3/4] " Pankaj Dubey
1 sibling, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2015-08-17 2:11 UTC (permalink / raw)
To: linux-arm-kernel
On 11.08.2015 12:46, Chanwoo Choi wrote:
> This patch add the uart2 devicetree node for Exynos3250 SoC.
"This patch adds the UART2 Device Tree node..."
>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
> arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
> 2 files changed, 19 insertions(+)
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/4] ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
2015-08-11 3:46 ` [PATCH 4/4] ARM: dts: Add MSHC2 " Chanwoo Choi
@ 2015-08-17 2:13 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2015-08-17 2:13 UTC (permalink / raw)
To: linux-arm-kernel
On 11.08.2015 12:46, Chanwoo Choi wrote:
> This patch add the MSHC2 (Mobile Storage Host Controller) devicetree node for
> Exynos3250 SoC.
s/add/adds/
s/devicetree/Device Tree/
>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
> 2 files changed, 48 insertions(+)
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* [1/4] clk: samsung: exynos3250: Add UART2 clock
2015-08-11 3:46 ` [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
2015-08-17 1:01 ` Krzysztof Kozlowski
@ 2015-08-17 3:29 ` Pankaj Dubey
1 sibling, 0 replies; 14+ messages in thread
From: Pankaj Dubey @ 2015-08-17 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chanwoo,
Thanks for this patch. Similar patch[1] was posted long back, and there
were some concern from your side, if you think those concerns are fixed,
then my patch [1] are still valid and can be taken. If it needs to be
rebase I am happy to do that.
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/291239.html
Thanks,
Pankaj Dubey
On Tuesday 11 August 2015 09:16 AM, Chanwoo Choi wrote:
> This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
>
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> ---
> drivers/clk/samsung/clk-exynos3250.c | 6 ++++++
> include/dt-bindings/clock/exynos3250.h | 6 +++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index 538de66a759e..2105863a3ace 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -307,6 +307,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
> MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
>
> /* SRC_PERIL0 */
> + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
> MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
> MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
>
> @@ -389,6 +390,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
> DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>
> /* DIV_PERIL0 */
> + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
> DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
>
> @@ -551,6 +553,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
> GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
> +
> + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
> + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
> GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
> @@ -648,6 +653,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
> GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
> GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
> GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
> + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
> GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
> GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
> };
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index aab088d30199..89a7d97b002c 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -78,6 +78,7 @@
> #define CLK_MOUT_CORE 58
> #define CLK_MOUT_APLL 59
> #define CLK_MOUT_ACLK_266_SUB 60
> +#define CLK_MOUT_UART2 61
>
> /* Dividers */
> #define CLK_DIV_GPL 64
> @@ -126,6 +127,7 @@
> #define CLK_DIV_CORE 107
> #define CLK_DIV_HPM 108
> #define CLK_DIV_COPY 109
> +#define CLK_DIV_UART2 110
>
> /* Gates */
> #define CLK_ASYNC_G3D 128
> @@ -222,6 +224,7 @@
> #define CLK_BLOCK_MFC 219
> #define CLK_BLOCK_CAM 220
> #define CLK_SMIES 221
> +#define CLK_UART2 222
>
> /* Special clocks */
> #define CLK_SCLK_JPEG 224
> @@ -248,12 +251,13 @@
> #define CLK_SCLK_SPI0 245
> #define CLK_SCLK_UART1 246
> #define CLK_SCLK_UART0 247
> +#define CLK_SCLK_UART2 248
>
> /*
> * Total number of clocks of main CMU.
> * NOTE: Must be equal to last clock ID increased by one.
> */
> -#define CLK_NR_CLKS 248
> +#define CLK_NR_CLKS 249
>
> /*
> * CMU DMC
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC
2015-08-11 3:46 ` [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
2015-08-17 2:11 ` Krzysztof Kozlowski
@ 2015-08-17 3:33 ` Pankaj Dubey
1 sibling, 0 replies; 14+ messages in thread
From: Pankaj Dubey @ 2015-08-17 3:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chanwoo,
Similar patch was posted here[1].
[1]:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/291023.html
Thanks,
Pankaj Dubey
On Tuesday 11 August 2015 09:16 AM, Chanwoo Choi wrote:
> This patch add the uart2 devicetree node for Exynos3250 SoC.
>
> Cc: Kukjin Kim <kgene@kernel.org>
> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
> ---
> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
> arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> index 5ab81c39e2c9..eac1d21c10d4 100644
> --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
> @@ -120,6 +120,13 @@
> samsung,pin-drv = <0>;
> };
>
> + uart2_data: uart2-data {
> + samsung,pins = "gpa1-0", "gpa1-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> i2c3_bus: i2c3-bus {
> samsung,pins = "gpa1-2", "gpa1-3";
> samsung,pin-function = <3>;
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 2db99433e17f..02f3250766c9 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -42,6 +42,7 @@
> i2c7 = &i2c_7;
> serial0 = &serial_0;
> serial1 = &serial_1;
> + serial2 = &serial_2;
> };
>
> cpus {
> @@ -435,6 +436,17 @@
> status = "disabled";
> };
>
> + serial_2: serial at 13820000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x13820000 0x100>;
> + interrupts = <0 111 0>;
> + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_data>;
> + status = "disabled";
> + };
> +
> i2c_0: i2c at 13860000 {
> #address-cells = <1>;
> #size-cells = <0>;
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2015-08-17 3:33 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-08-11 3:46 [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Chanwoo Choi
2015-08-11 3:46 ` [PATCH 1/4] clk: samsung: exynos3250: Add UART2 clock Chanwoo Choi
2015-08-17 1:01 ` Krzysztof Kozlowski
2015-08-17 3:29 ` [1/4] " Pankaj Dubey
2015-08-11 3:46 ` [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock Chanwoo Choi
2015-08-17 1:48 ` Krzysztof Kozlowski
2015-08-11 3:46 ` [PATCH 3/4] ARM: dts: Add UART2 dt node for Exynos3250 SoC Chanwoo Choi
2015-08-17 2:11 ` Krzysztof Kozlowski
2015-08-17 3:33 ` [3/4] " Pankaj Dubey
2015-08-11 3:46 ` [PATCH 4/4] ARM: dts: Add MSHC2 " Chanwoo Choi
2015-08-17 2:13 ` Krzysztof Kozlowski
2015-08-17 0:33 ` [PATCH 0/4] ARM: dts: exynos3250: Add UART2 and MMC2 dt node with related clocks Krzysztof Kozlowski
2015-08-17 0:36 ` Chanwoo Choi
2015-08-17 0:37 ` Krzysztof Kozlowski
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