* [PATCH 1/5] mmc: sdhci-pxav3: Enable pxa1928 device support
2015-09-04 15:32 [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
@ 2015-09-04 15:32 ` Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 2/5] mmc: sdhci-pxav3: Add platform specific set_clock ops Vaibhav Hiremath
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Vaibhav Hiremath @ 2015-09-04 15:32 UTC (permalink / raw)
To: linux-arm-kernel
SDHCI controller present in PXA1928 has few differences as far as
register map is concerned.
For example,
PXAxxx PXA1928
====== =======
SDCLK_DELAY field 0x10A 0x114
SDCLK_DELAY mask 0x1F 0x3FF
SDCLK_DELAY shift 9 8
SDCLK_SEL shift 8 2 (SEL1)
So in order to support multi-platform, use sdhci_pxa_regdata structure
as a variant data according to platform.
Note that, there are some more differences, which would be added
as and when respective feature gets added to the driver.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
---
drivers/mmc/host/sdhci-pxav3.c | 62 ++++++++++++++++++++++++++++++++++--------
1 file changed, 51 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 6d4bad4..aecae04 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -42,9 +42,6 @@
#define PXAV3_RPM_DELAY_MS 50
#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
-#define SDCLK_SEL 0x100
-#define SDCLK_DELAY_SHIFT 9
-#define SDCLK_DELAY_MASK 0x1f
#define SD_CFG_FIFO_PARAM 0x100
#define SDCFG_GEN_PAD_CLK_ON BIT(6)
@@ -58,11 +55,25 @@
#define SDCE_MISC_INT BIT(2)
#define SDCE_MISC_INT_EN BIT(1)
+#define SD_RX_CFG_REG 0x114
+
/* IO Power control */
#define IO_PWR_AKEY_ASFAR 0xbaba
#define IO_PWR_AKEY_ASSAR 0xeb10
#define IO_PWR_MMC1_PAD_1V8 BIT(2)
+struct sdhci_pxa_data {
+ u32 sdclk_delay_reg;
+ u32 sdclk_delay_mask;
+ u8 sdclk_delay_shift;
+ u8 sdclk_sel_mask;
+ u8 sdclk_sel_shift;
+ /*
+ * We have few more differences, add them along with their
+ * respective feature support
+ */
+};
+
struct sdhci_pxa {
struct clk *clk_core;
struct clk *clk_io;
@@ -70,6 +81,24 @@ struct sdhci_pxa {
void __iomem *sdio3_conf_reg;
void __iomem *io_pwr_reg;
void __iomem *io_pwr_lock_reg;
+ struct sdhci_pxa_data *data;
+};
+
+static struct sdhci_pxa_data pxav3_data_v1 = {
+ .sdclk_delay_reg = SD_CLOCK_BURST_SIZE_SETUP,
+ .sdclk_delay_mask = 0x1F,
+ .sdclk_delay_shift = 9,
+ .sdclk_sel_mask = 0x1,
+ .sdclk_sel_shift = 8,
+};
+
+static struct sdhci_pxa_data pxav3_data_v2 = {
+ .sdclk_delay_reg = SD_RX_CFG_REG,
+ .sdclk_delay_mask = 0x3FF,
+ .sdclk_delay_shift = 8,
+ /* Only set SDCLK_SEL1, as driver uses default value of SDCLK_SEL0 */
+ .sdclk_sel_mask = 0x3,
+ .sdclk_sel_shift = 2, /* SDCLK_SEL1 */
};
/*
@@ -183,6 +212,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
sdhci_reset(host, mask);
@@ -193,12 +224,14 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
*/
if (pdata && 0 != pdata->clk_delay_cycles) {
u16 tmp;
-
- tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
- tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
- << SDCLK_DELAY_SHIFT;
- tmp |= SDCLK_SEL;
- writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
+ struct sdhci_pxa_data *data = pxa->data;
+
+ tmp = readw(host->ioaddr + data->sdclk_delay_reg);
+ tmp |= (pdata->clk_delay_cycles & data->sdclk_delay_mask)
+ << data->sdclk_delay_shift;
+ tmp &= ~(data->sdclk_sel_mask << data->sdclk_sel_shift);
+ tmp |= 1 << data->sdclk_sel_shift;
+ writew(tmp, host->ioaddr + data->sdclk_delay_reg);
}
}
}
@@ -363,10 +396,16 @@ static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
{
- .compatible = "mrvl,pxav3-mmc",
+ .compatible = "mrvl,pxav3-mmc",
+ .data = (void *)&pxav3_data_v1,
+ },
+ {
+ .compatible = "marvell,armada-380-sdhci",
+ .data = (void *)&pxav3_data_v1,
},
{
- .compatible = "marvell,armada-380-sdhci",
+ .compatible = "marvell,pxav3-1928-sdhci",
+ .data = (void *)&pxav3_data_v2,
},
{},
};
@@ -470,6 +509,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
goto err_of_parse;
sdhci_get_of_property(pdev);
pdata = pxav3_get_mmc_pdata(dev);
+ pxa->data = (struct sdhci_pxa_data *)match->data;
pdev->dev.platform_data = pdata;
} else if (pdata) {
/* on-chip device */
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] mmc: sdhci-pxav3: Add platform specific set_clock ops
2015-09-04 15:32 [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 1/5] mmc: sdhci-pxav3: Enable pxa1928 device support Vaibhav Hiremath
@ 2015-09-04 15:32 ` Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock Vaibhav Hiremath
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Vaibhav Hiremath @ 2015-09-04 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In case of PXA1928 & family of devices, the TX BUS and internal clock
need to be set as part of ->set_clock() ops, so this patch adds
platform specific ->set_clock() operation.
Note that, in order to not break other platforms, this patch
introduced the flag, which controls whether controller/platform
specific clock configuration needs to be executed.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
---
drivers/mmc/host/sdhci-pxav3.c | 46 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index aecae04..c2b2b78 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -48,6 +48,10 @@
#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
+#define SD_FIFO_PARAM 0x104
+#define INTERNAL_CLK_GATE_CTRL BIT(8)
+#define INTERNAL_CLK_GATE_ON BIT(9)
+
#define SD_SPI_MODE 0x108
#define SD_CE_ATA_1 0x10C
@@ -57,6 +61,9 @@
#define SD_RX_CFG_REG 0x114
+#define TX_CFG_REG 0x118
+#define TX_INTERNAL_SEL_BUS_CLK BIT(30)
+
/* IO Power control */
#define IO_PWR_AKEY_ASFAR 0xbaba
#define IO_PWR_AKEY_ASSAR 0xeb10
@@ -68,6 +75,9 @@ struct sdhci_pxa_data {
u8 sdclk_delay_shift;
u8 sdclk_sel_mask;
u8 sdclk_sel_shift;
+
+ /* set this if platform needs separate clock configuration */
+ bool set_pltfrm_clk;
/*
* We have few more differences, add them along with their
* respective feature support
@@ -90,6 +100,7 @@ static struct sdhci_pxa_data pxav3_data_v1 = {
.sdclk_delay_shift = 9,
.sdclk_sel_mask = 0x1,
.sdclk_sel_shift = 8,
+ .set_pltfrm_clk = false,
};
static struct sdhci_pxa_data pxav3_data_v2 = {
@@ -99,6 +110,7 @@ static struct sdhci_pxa_data pxav3_data_v2 = {
/* Only set SDCLK_SEL1, as driver uses default value of SDCLK_SEL0 */
.sdclk_sel_mask = 0x3,
.sdclk_sel_shift = 2, /* SDCLK_SEL1 */
+ .set_pltfrm_clk = true,
};
/*
@@ -375,8 +387,40 @@ static void pxav3_voltage_switch(struct sdhci_host *host,
writel(val, pxa->io_pwr_reg);
}
+static void pxav3_set_tx_clock(struct sdhci_host *host)
+{
+ u32 val;
+
+ val = sdhci_readl(host, TX_CFG_REG);
+ val |= TX_INTERNAL_SEL_BUS_CLK;
+ sdhci_writel(host, val, TX_CFG_REG);
+}
+
+static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+
+ /* We still use common sdhci_set_clock() */
+ sdhci_set_clock(host, clock);
+
+ /* platform/controller specific clock configuration */
+ if (pxa->data->set_pltfrm_clk && clock != 0) {
+ u32 val;
+
+ val = sdhci_readw(host, SD_FIFO_PARAM);
+ /* Internal clock gate ON and CTRL = 0b11 */
+ val |= INTERNAL_CLK_GATE_CTRL | INTERNAL_CLK_GATE_ON;
+ sdhci_writew(host, val, SD_FIFO_PARAM);
+
+ /* TX internal clock selection */
+ pxav3_set_tx_clock(host);
+ }
+
+}
+
static const struct sdhci_ops pxav3_sdhci_ops = {
- .set_clock = sdhci_set_clock,
+ .set_clock = pxav3_set_clock,
.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.set_bus_width = sdhci_set_bus_width,
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock
2015-09-04 15:32 [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 1/5] mmc: sdhci-pxav3: Enable pxa1928 device support Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 2/5] mmc: sdhci-pxav3: Add platform specific set_clock ops Vaibhav Hiremath
@ 2015-09-04 15:32 ` Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support Vaibhav Hiremath
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Vaibhav Hiremath @ 2015-09-04 15:32 UTC (permalink / raw)
To: linux-arm-kernel
Different bus clock may need different pin setting.
For example, fast bus clock like 208Mhz need pin drive fast
while slow bus clock prefer pin drive slow to guarantee
signal quality.
So this patch creates two states,
- Default (slow/normal) pin state
- And fast pin state for higher freq bus speed.
And selection of pin state is done based on timing mode.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Kevin Liu <kliu5@marvell.com>
---
drivers/mmc/host/sdhci-pxav3.c | 45 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index c2b2b78..d933f75 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -35,6 +35,7 @@
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/mbus.h>
+#include <linux/pinctrl/consumer.h>
#include "sdhci.h"
#include "sdhci-pltfm.h"
@@ -92,6 +93,10 @@ struct sdhci_pxa {
void __iomem *io_pwr_reg;
void __iomem *io_pwr_lock_reg;
struct sdhci_pxa_data *data;
+
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pins_default;
+ struct pinctrl_state *pins_fast;
};
static struct sdhci_pxa_data pxav3_data_v1 = {
@@ -298,6 +303,33 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
pxa->power_mode = power_mode;
}
+static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_pxa *pxa = pltfm_host->priv;
+ struct pinctrl_state *pinctrl;
+
+ if (IS_ERR(pxa->pinctrl) ||
+ IS_ERR(pxa->pins_default) ||
+ IS_ERR(pxa->pins_fast))
+ return -EINVAL;
+
+ switch (uhs) {
+ case MMC_TIMING_UHS_SDR50:
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
+ pinctrl = pxa->pins_fast;
+ break;
+ default:
+ /* back to default state for other legacy timing */
+ pinctrl = pxa->pins_default;
+ break;
+ }
+
+ return pinctrl_select_state(pxa->pinctrl, pinctrl);
+}
+
static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -353,6 +385,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
dev_dbg(mmc_dev(host->mmc),
"%s uhs = %d, ctrl_2 = %04X\n",
__func__, uhs, ctrl_2);
+
+ pxav3_select_pinstate(host, uhs);
}
static void pxav3_voltage_switch(struct sdhci_host *host,
@@ -416,7 +450,6 @@ static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock)
/* TX internal clock selection */
pxav3_set_tx_clock(host);
}
-
}
static const struct sdhci_ops pxav3_sdhci_ops = {
@@ -586,6 +619,16 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
}
}
+ pxa->pinctrl = devm_pinctrl_get(dev);
+ if (!IS_ERR(pxa->pinctrl)) {
+ pxa->pins_default = pinctrl_lookup_state(pxa->pinctrl, "default");
+ if (IS_ERR(pxa->pins_default))
+ dev_err(dev, "could not get default pinstate\n");
+ pxa->pins_fast = pinctrl_lookup_state(pxa->pinctrl, "fast");
+ if (IS_ERR(pxa->pins_fast))
+ dev_info(dev, "could not get fast pinstate\n");
+ }
+
pm_runtime_get_noresume(&pdev->dev);
pm_runtime_set_active(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support
2015-09-04 15:32 [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
` (2 preceding siblings ...)
2015-09-04 15:32 ` [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock Vaibhav Hiremath
@ 2015-09-04 15:32 ` Vaibhav Hiremath
2015-09-04 15:32 ` [PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields Vaibhav Hiremath
2015-09-07 10:36 ` [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
5 siblings, 0 replies; 7+ messages in thread
From: Vaibhav Hiremath @ 2015-09-04 15:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Kevin Liu <kliu5@marvell.com>
IN case of MMC HS200 mode, current code does not enable
SD_CE_ATA_2.MMC_HS200 & SD_CE_ATA_2.MMC_CARD bit configurations.
So this patch updates the above bit fields correctly.
Signed-off-by: Tim Wang <wangtt@marvell.com>
Signed-off-by: Kevin Liu <kliu5@marvell.com>
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
---
Note: Unfortunately I do not have access to any other datasheets
which uses sdhci-pxav3 driver, so quite not sure whether this would
break any existing platform, probably NOT, as I do not see any
references for this change.
If anyone can confirm that would be really great.
drivers/mmc/host/sdhci-pxav3.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index d933f75..6978810 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -57,6 +57,8 @@
#define SD_CE_ATA_1 0x10C
#define SD_CE_ATA_2 0x10E
+#define SD_CE_ATA2_HS200_EN BIT(10)
+#define SD_CE_ATA2_MMC_MODE BIT(12)
#define SDCE_MISC_INT BIT(2)
#define SDCE_MISC_INT_EN BIT(1)
@@ -330,6 +332,17 @@ static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs)
return pinctrl_select_state(pxa->pinctrl, pinctrl);
}
+static int pxav3_select_hs200(struct sdhci_host *host)
+{
+ u16 reg = 0;
+
+ reg = sdhci_readw(host, SD_CE_ATA_2);
+ reg |= SD_CE_ATA2_HS200_EN | SD_CE_ATA2_MMC_MODE;
+ sdhci_writew(host, reg, SD_CE_ATA_2);
+
+ return 0;
+}
+
static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -361,6 +374,10 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
case MMC_TIMING_UHS_DDR50:
ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
break;
+ case MMC_TIMING_MMC_HS200:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+ pxav3_select_hs200(host);
+ break;
}
/*
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields
2015-09-04 15:32 [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
` (3 preceding siblings ...)
2015-09-04 15:32 ` [PATCH 4/5] mmc: sdhci-pxav3: Fix HS200 mode support Vaibhav Hiremath
@ 2015-09-04 15:32 ` Vaibhav Hiremath
2015-09-07 10:36 ` [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
5 siblings, 0 replies; 7+ messages in thread
From: Vaibhav Hiremath @ 2015-09-04 15:32 UTC (permalink / raw)
To: linux-arm-kernel
IN case of Marvell 1928 family of devices, the SD_BUS_POWER and
SD_BUS_VLT bits are used internally to gate the clocks, so
we have to set these fields.
Pasting Spec words here,
The <SD_BUS_VLT> and <SD_BUS_POWER> fields should be configured
to correct values. These actually do not do the voltage selection
or switch power to the SD card. However these fields are used
internally to gate the clock. So if these fields are set
incorrectly, SD module will not function.
And during my development, I have seen that SD card wouldn't function
without right configuration into these fields.
So this patch adds new quirk (SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER),
which make sure that ->set_power() sets these fields.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
---
drivers/mmc/host/sdhci-pltfm.c | 3 +++
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 2 ++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index a207f5a..0872da0 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -101,6 +101,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
of_device_is_compatible(np, "fsl,mpc8536-esdhc"))
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+ if (of_device_is_compatible(np, "marvell,pxav3-988-sdhci"))
+ host->quirks2 |= SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER;
+
clk = of_get_property(np, "clock-frequency", &size);
if (clk && size == sizeof(*clk) && *clk)
pltfm_host->clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 2d58b31..418f381 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1265,7 +1265,8 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
else
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
- return;
+ if (!(host->quirks2 | SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER))
+ return;
}
if (mode != MMC_POWER_OFF) {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 9b0e2a8..8802a0c 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -409,6 +409,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
/* Controller broken with using ACMD23 */
#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
+/* Voltage capabilities of Controller must be set */
+#define SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER (1<<15)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller
2015-09-04 15:32 [PATCH 0/5] mmc: sdhci-pxav3: Enable support for PXA1928 SDCHI controller Vaibhav Hiremath
` (4 preceding siblings ...)
2015-09-04 15:32 ` [PATCH 5/5] mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields Vaibhav Hiremath
@ 2015-09-07 10:36 ` Vaibhav Hiremath
5 siblings, 0 replies; 7+ messages in thread
From: Vaibhav Hiremath @ 2015-09-07 10:36 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 04 September 2015 09:02 PM, Vaibhav Hiremath wrote:
> PXA1928 SDHCI controller has few differences, for example,
>
> PXAxxx PXA1928
> ====== =======
> SDCLK_DELAY field 0x10A 0x114
> SDCLK_DELAY mask 0x1F 0x3FF
> SDCLK_DELAY shift 9 8
> SDCLK_SEL shift 8 2 (SEL1)
>
> So this patch series introduces new compatible device_id
> (marvell,pxav3-1928-sdhci), and makes use of .data for handling
> such differences.
>
> The series also adds support like,
>
> - independent ->set_clock() api, as we need to enable internal clock gate
> and TX clock
> - pinctrl configuration based on bus speed.
> - introduce new quirk SDHCI_QUIRK2_MUST_SET_SDHCI_BUS_POWER
> SD_BUS_POWER & SD_BUS_VLT bit-fields are used internally to gate the
> clocks, so it is important to configure them as part of ->set_power()
> More detailed description is written into commit log.
> - Enable SDHCI_QUIRK_BROKEN_TIMEOUT_VAL for PXA1928 device_id
>
Please ignore this series, as one residual change (rather typo error).
Mistakenly while checking in the code, instead of 1928 compatible
property it was 988.
I will submit the new series shortly.
Thanks,
Vaibhav
>
> Testing:
> I have done basic testing on both eMMC and SD card on PXA1928 based
> platform.
>
> Note: I tried to made sure that I do not break any other platform, which
> used sdhci, except HS200 configuration.
> Unfortunately I do not have access to any other datasheets, where I can
> cross check the details on HS200 bit-fields. Probably someone who has
> access can confirm [PATCH 4/5], whether it impacts other platforms.
>
> Kevin Liu (1):
> mmc: sdhci-pxav3: Fix HS200 mode support
>
> Vaibhav Hiremath (4):
> mmc: sdhci-pxav3: Enable pxa1928 device support
> mmc: sdhci-pxav3: Add platform specific set_clock ops
> mmc: sdhci-pxav3: Add pinctl setting according to bus clock
> mmc: sdhci: add new quirk for setting BUS_POWER & BUS_VLT fields
>
> drivers/mmc/host/sdhci-pltfm.c | 3 +
> drivers/mmc/host/sdhci-pxav3.c | 168 ++++++++++++++++++++++++++++++++++++++---
> drivers/mmc/host/sdhci.c | 3 +-
> drivers/mmc/host/sdhci.h | 2 +
> 4 files changed, 163 insertions(+), 13 deletions(-)
>
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