[PATCH 0/3] arm64 fixes following support for hardware AF/DBM

[PATCH 0/3] arm64 fixes following support for hardware AF/DBM

[Catalin Marinas]

It seems that the recent patch for handling hardware updates to the AF
and dirty bits also breaks hardware without such feature because of
changes to how a pte is detected as dirty. The first patch fixes the
non-DBM hardware case. The second is fixes losing of the dirty
information for hardware DBM (as a consequence of the first patch,
otherwise a pte was pretty much always dirty anyway). The third patch is
a clean-up.

Catalin Marinas (2):
  arm64: Fix the pte_hw_dirty() check when AF/DBM is enabled
  arm64: Fix pte_modify() to preserve the hardware dirty information

Will Deacon (1):
  arm64: pgtable: use a single bit for PTE_WRITE regardless of DBM

 arch/arm64/include/asm/pgtable.h | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

[PATCH 1/3] arm64: Fix the pte_hw_dirty() check when AF/DBM is enabled

[Catalin Marinas]

Commit 2f4b829c625e (arm64: Add support for hardware updates of the
access and dirty pte bits) introduced support for handling hardware
updates of the access flag and dirty status. The PTE is automatically
dirtied in hardware (if supported) by clearing the PTE_RDONLY bit when
the PTE_DBM/PTE_WRITE bit is set. The pte_hw_dirty() macro was added to
detect a hardware dirtied pte. The pte_dirty() macro checks for both
software PTE_DIRTY and pte_hw_dirty().

Functions like pte_modify() clear the PTE_RDONLY bit since it is meant
to be set in set_pte_at() when written to memory. In such cases,
pte_hw_dirty() would return true even though such pte is clean. This
patch changes pte_hw_dirty() to test the PTE_DBM/PTE_WRITE bit together
with PTE_RDONLY.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Julien Grall <julien.grall@citrix.com>
Cc: Will Deacon <will.deacon@arm.com>
Fixes: 2f4b829c625e ("arm64: Add support for hardware updates of the access and dirty pte bits")
---
 arch/arm64/include/asm/pgtable.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 6900b2d95371..69207f016891 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -146,7 +146,7 @@ extern struct page *empty_zero_page;
 #define pte_exec(pte)		(!(pte_val(pte) & PTE_UXN))
 
 #ifdef CONFIG_ARM64_HW_AFDBM
-#define pte_hw_dirty(pte)	(!(pte_val(pte) & PTE_RDONLY))
+#define pte_hw_dirty(pte)	(pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
 #else
 #define pte_hw_dirty(pte)	(0)
 #endif
@@ -238,7 +238,7 @@ extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
  * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
  * the page fault mechanism. Checking the dirty status of a pte becomes:
  *
- *   PTE_DIRTY || !PTE_RDONLY
+ *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
  */
 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 			      pte_t *ptep, pte_t pte)

[PATCH 2/3] arm64: Fix pte_modify() to preserve the hardware dirty information

[Catalin Marinas]

The pte_modify() function with hardware AF/DBM enabled must transfer the
hardware dirty information to the software PTE_DIRTY bit. However, it
was setting this bit in newprot and the mask does not cover such bit.
This patch sets PTE_DIRTY on the original pte which will be preserved in
the returned value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Julien Grall <julien.grall@citrix.com>
Fixes: 2f4b829c625e ("arm64: Add support for hardware updates of the access and dirty pte bits")
---
 arch/arm64/include/asm/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 69207f016891..31df98adf005 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -503,7 +503,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 			      PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
 	/* preserve the hardware dirty information */
 	if (pte_hw_dirty(pte))
-		newprot |= PTE_DIRTY;
+		pte = pte_mkdirty(pte);
 	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
 	return pte;
 }

[PATCH 3/3] arm64: pgtable: use a single bit for PTE_WRITE regardless of DBM

[Catalin Marinas]

From: Will Deacon <will.deacon@arm.com>

Depending on CONFIG_ARM64_HW_AFDBM, we use either bit 57 or 51 of the
pte to represent PTE_WRITE. Given that bit 51 is reserved prior to
ARMv8.1, we can just use that bit regardless of the config option. That
also matches what happens if a kernel configured with ARM64_HW_AFDBM=y
is run on a CPU without the DBM functionality.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Julien Grall <julien.grall@citrix.com>
---
 arch/arm64/include/asm/pgtable.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 31df98adf005..b0329be95cb1 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -26,13 +26,9 @@
  * Software defined PTE bits definition.
  */
 #define PTE_VALID		(_AT(pteval_t, 1) << 0)
+#define PTE_WRITE		(PTE_DBM)		 /* same as DBM (51) */
 #define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
 #define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
-#ifdef CONFIG_ARM64_HW_AFDBM
-#define PTE_WRITE		(PTE_DBM)		 /* same as DBM */
-#else
-#define PTE_WRITE		(_AT(pteval_t, 1) << 57)
-#endif
 #define PTE_PROT_NONE		(_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
 
 /*

[PATCH 0/3] arm64 fixes following support for hardware AF/DBM

[Julien Grall]

Hi Catalin,

On 11/09/15 18:21, Catalin Marinas wrote:
> It seems that the recent patch for handling hardware updates to the AF
> and dirty bits also breaks hardware without such feature because of
> changes to how a pte is detected as dirty. The first patch fixes the
> non-DBM hardware case. The second is fixes losing of the dirty
> information for hardware DBM (as a consequence of the first patch,
> otherwise a pte was pretty much always dirty anyway). The third patch is
> a clean-up.

Thank you, this series is fixing the userspace issue on X-gene:

Tested-by: Julien Grall <julien.grall@citrix.com>

Regards,

-- 
Julien Grall