Re: [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1

From: Chanwoo Choi <cwchoi00@gmail.com>
To: Chanho Park <chanho61.park@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Alim Akhtar <alim.akhtar@samsung.com>,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
Date: Thu, 30 Jun 2022 04:36:50 +0900	[thread overview]
Message-ID: <56235075-6cf5-adb5-ff9f-0e762d2455ef@gmail.com> (raw)
In-Reply-To: <20220628104138.152118-3-chanho61.park@samsung.com>

On 22. 6. 28. 19:41, Chanho Park wrote:
> "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
> and peric1 respectively.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index d9e1f8e4a7b4..c5a4e1bee711 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
>  	     "mout_peric0_bus_user",
>  	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
>  	     21, 0, 0),
> +	GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
> +	     "mout_peric0_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
> +	     21, 0, 0),
>  	GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
>  	     "mout_peric0_bus_user",
>  	     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
> @@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
>  	     "mout_peric1_bus_user",
>  	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
>  	     21, 0, 0),
> +	GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
> +	     "mout_peric1_bus_user",
> +	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
> +	     21, 0, 0),
>  	GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
>  	     "mout_peric1_bus_user",
>  	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

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