From: wangzhou1@hisilicon.com (Zhou Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v11 1/6] PCI: designware: move calculation of bus addresses to DRA7xx
Date: Mon, 26 Oct 2015 15:27:14 +0800 [thread overview]
Message-ID: <562DD5D2.9000705@hisilicon.com> (raw)
In-Reply-To: <20151022163534.GB21237@localhost>
On 2015/10/23 0:35, Bjorn Helgaas wrote:
> Hi Gabriele,
>
> On Thu, Oct 22, 2015 at 07:21:41AM +0000, Gabriele Paoloni wrote:
>>> -----Original Message-----
>>> From: Bjorn Helgaas [mailto:helgaas at kernel.org]
>
>>>> #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
>>>> #define LINK_UP BIT(16)
>>>> +#define CPU_TO_BUS_ADDR 0x0FFFFFFF
>>>
>>> "CPU_TO_BUS_ADDR" is a very generic name. Since you do have DRA7XX in
>>> other #defines and static symbols in this file, maybe it could be DRA7XX to
>>> make it obvious that it only applies here?
>>
>> Ok will change to DRA7XX_CPU_TO_BUS_ADRR in v12
>> ..
>
>>>> + if (pp->io_mod_base)
>>>> + pp->io_mod_base &= CPU_TO_BUS_ADDR;
>>>
>>> These are equivalent to
>>>
>>> pp->io_mod_base &= CPU_TO_BUS_ADDR;
>>>
>>> (You don't need to test whether they're zero first.)
>>
>> Yes agreed, will change in v12
>> ...
>
>>>> cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
>>>> @@ -415,8 +411,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>>>> pp->io_base = range.cpu_addr;
>>>>
>>>> /* Find the untranslated IO space address */
>>>> - pp->io_mod_base = of_read_number(parser.range -
>>>> - parser.np + na, ns);
>>>> + pp->io_mod_base = range.cpu_addr;
>>>
>>> So apparently
>>>
>>> "of_read_number() == range.cpu_addr & CPU_TO_BUS_ADDR" on DRA7xx
>>> "of_read_number() == range.cpu_addr" everywhere else?
>>
>> Yes correct
>>
>>> Is that right? Is that a valid assumption, i.e., are we assuming
>>> anything about DTs in the field that we shouldn't?
>>
>> Before I wrote a patch that was generic to accommodate intermediate level
>> of translation between PCI_addr -> BUS_addr -> CPU_addr
>>
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/360922.html
>>
>> After discussion we agreed to solve it with a bitmask rather than adding
>> a field to of_pci_range to make it generic.
>> The bitmask only applies to DRA7xx
>
> I haven't gotten all the way through this series yet, but don't bother with
> a v12 just for these minor changes. I can easily fix them up when applying
> it.
>
> Bjorn
>
Hi Gabriele and Bjorn,
Sorry for late, I am preparing v12 patchset and I will fix above problems together
with other patches.
Many thanks,
Zhou
> .
>
next prev parent reply other threads:[~2015-10-26 7:27 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 10:23 [PATCH v11 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-10-16 10:23 ` [PATCH v11 1/6] PCI: designware: move calculation of bus addresses to DRA7xx Zhou Wang
2015-10-21 22:15 ` Bjorn Helgaas
2015-10-22 7:21 ` Gabriele Paoloni
2015-10-22 16:35 ` Bjorn Helgaas
2015-10-22 16:37 ` Gabriele Paoloni
2015-10-26 7:27 ` Zhou Wang [this message]
2015-10-16 10:23 ` [PATCH v11 2/6] ARM/PCI: remove align_resource in pci_sys_data Zhou Wang
2015-10-16 10:23 ` [PATCH v11 3/6] PCI: designware: Add ARM64 support Zhou Wang
2015-10-22 18:28 ` Bjorn Helgaas
2015-10-26 7:37 ` Zhou Wang
2015-10-16 10:23 ` [PATCH v11 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-10-22 18:46 ` Bjorn Helgaas
2015-10-26 8:24 ` Zhou Wang
2015-10-16 10:23 ` [PATCH v11 5/6] Documentation: DT: Add HiSilicon PCIe host binding Zhou Wang
2015-10-16 10:23 ` [PATCH v11 6/6] MAINTAINERS: Add pcie-hisi maintainer Zhou Wang
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