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From: cov@codeaurora.org (Christopher Covington)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register
Date: Mon, 02 Nov 2015 15:54:12 -0500	[thread overview]
Message-ID: <5637CD74.2010609@codeaurora.org> (raw)
In-Reply-To: <1446186123-11548-9-git-send-email-zhaoshenglong@huawei.com>

Hi Shannon,

On 10/30/2015 02:21 AM, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
> 
> Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or
> reset_unknown_cp15 for its reset handler. Add access handler which
> emulates writing and reading PMXEVTYPER register. When writing to
> PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event
> for the selected event type.
> 
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
>  arch/arm64/kvm/sys_regs.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index cb82b15..4e606ea 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -491,6 +491,17 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
>  
>  	if (p->is_write) {
>  		switch (r->reg) {
> +		case PMXEVTYPER_EL0: {
> +			val = vcpu_sys_reg(vcpu, PMSELR_EL0);
> +			kvm_pmu_set_counter_event_type(vcpu,
> +						       *vcpu_reg(vcpu, p->Rt),
> +						       val);
> +			vcpu_sys_reg(vcpu, PMXEVTYPER_EL0) =
> +							 *vcpu_reg(vcpu, p->Rt);

Why does PMXEVTYPER get set directly? It seems like it could have an accessor
that redirected to PMEVTYPER<n>.

> +			vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + val) =
> +							 *vcpu_reg(vcpu, p->Rt);

I tried to look around briefly but couldn't find counter number range checking
in the PMSELR handler or here. Should there be some here and in PMXEVCNTR?

Thanks,
Christopher Covington

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2015-11-02 20:54 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-30  6:21 [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-11-30 18:11   ` Marc Zyngier
2015-10-30  6:21 ` [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-11-02 20:06   ` Christopher Covington
2015-11-30 17:56   ` Marc Zyngier
2015-12-01  1:51     ` Shannon Zhao
2015-12-01  8:49       ` Marc Zyngier
2015-12-01 12:46         ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-11-30 11:42   ` Marc Zyngier
2015-11-30 11:59     ` Shannon Zhao
2015-11-30 13:19       ` Marc Zyngier
2015-10-30  6:21 ` [PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-11-02 20:13   ` Christopher Covington
2015-11-03  2:33     ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-11-02 20:54   ` Christopher Covington [this message]
2015-11-03  2:41     ` Shannon Zhao
2015-11-30 18:12   ` Marc Zyngier
2015-12-01  2:42     ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-11-02 21:20   ` Christopher Covington
2015-10-30  6:22 ` [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-10-30 12:08   ` kbuild test robot
2015-10-31  2:06     ` Shannon Zhao
2015-11-30 18:22   ` Marc Zyngier
2015-12-01 14:35     ` Shannon Zhao
2015-12-01 14:50       ` Marc Zyngier
2015-12-01 15:13         ` Shannon Zhao
2015-12-01 15:41           ` Marc Zyngier
2015-12-01 16:26             ` Shannon Zhao
2015-12-01 16:57               ` Marc Zyngier
2015-12-02  2:40                 ` Shannon Zhao
2015-12-02  8:45                   ` Marc Zyngier
2015-12-02  9:49                     ` Shannon Zhao
2015-12-02 10:22                       ` Marc Zyngier
2015-12-02 16:27                         ` Christoffer Dall
2015-10-30  6:22 ` [PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-10-30  6:22 ` [PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-10-30  6:22 ` [PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-11-30 18:31   ` Marc Zyngier
2015-11-30 18:34 ` [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-12-01  1:52   ` Shannon Zhao

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