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From: shannon.zhao@linaro.org (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing
Date: Tue, 01 Dec 2015 23:13:57 +0800	[thread overview]
Message-ID: <565DB935.5040609@linaro.org> (raw)
In-Reply-To: <565DB3A5.3030701@arm.com>



On 2015/12/1 22:50, Marc Zyngier wrote:
> On 01/12/15 14:35, Shannon Zhao wrote:
>>
>>
>> On 2015/12/1 2:22, Marc Zyngier wrote:
>>> On Fri, 30 Oct 2015 14:22:00 +0800
>>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>>
>>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>>
>>>> When calling perf_event_create_kernel_counter to create perf_event,
>>>> assign a overflow handler. Then when perf event overflows, set
>>>> irq_pending and call kvm_vcpu_kick() to sync the interrupt.
>>>>
>>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>> ---
>>>>   arch/arm/kvm/arm.c    |  4 +++
>>>>   include/kvm/arm_pmu.h |  4 +++
>>>>   virt/kvm/arm/pmu.c    | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++-
>>>>   3 files changed, 83 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>>>> index 78b2869..9c0fec4 100644
>>>> --- a/arch/arm/kvm/arm.c
>>>> +++ b/arch/arm/kvm/arm.c
>>>> @@ -28,6 +28,7 @@
>>>>   #include <linux/sched.h>
>>>>   #include <linux/kvm.h>
>>>>   #include <trace/events/kvm.h>
>>>> +#include <kvm/arm_pmu.h>
>>>>
>>>>   #define CREATE_TRACE_POINTS
>>>>   #include "trace.h"
>>>> @@ -551,6 +552,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
>>>>
>>>>   		if (ret <= 0 || need_new_vmid_gen(vcpu->kvm)) {
>>>>   			local_irq_enable();
>>>> +			kvm_pmu_sync_hwstate(vcpu);
>>>
>>> This is very weird. Are you only injecting interrupts when a signal is
>>> pending? I don't understand how this works...
>>>
>>>>   			kvm_vgic_sync_hwstate(vcpu);
>>>>   			preempt_enable();
>>>>   			kvm_timer_sync_hwstate(vcpu);
>>>> @@ -598,6 +600,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
>>>>   		kvm_guest_exit();
>>>>   		trace_kvm_exit(kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu));
>>>>
>>>> +		kvm_pmu_post_sync_hwstate(vcpu);
>>>> +
>>>>   		kvm_vgic_sync_hwstate(vcpu);
>>>>
>>>>   		preempt_enable();
>>>> diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
>>>> index acd025a..5e7f943 100644
>>>> --- a/include/kvm/arm_pmu.h
>>>> +++ b/include/kvm/arm_pmu.h
>>>> @@ -39,6 +39,8 @@ struct kvm_pmu {
>>>>   };
>>>>
>>>>   #ifdef CONFIG_KVM_ARM_PMU
>>>> +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
>>>> +void kvm_pmu_post_sync_hwstate(struct kvm_vcpu *vcpu);
>>>
>>> Please follow the current terminology: _flush_ on VM entry, _sync_ on
>>> VM exit.
>>>
>>
>> Hi Marc,
>>
>> Is below patch the right way for this?
>>
>> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>> index 78b2869..84008d1 100644
>> --- a/arch/arm/kvm/arm.c
>> +++ b/arch/arm/kvm/arm.c
>> @@ -28,6 +28,7 @@
>>   #include <linux/sched.h>
>>   #include <linux/kvm.h>
>>   #include <trace/events/kvm.h>
>> +#include <kvm/arm_pmu.h>
>>
>>   #define CREATE_TRACE_POINTS
>>   #include "trace.h"
>> @@ -531,6 +532,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu,
>> struct kvm_run *run)
>>                   */
>>                  kvm_timer_flush_hwstate(vcpu);
>>
>> +               kvm_pmu_flush_hwstate(vcpu);
>> +
>>                  /*
>>                   * Preparing the interrupts to be injected also
>>                   * involves poking the GIC, which must be done in a
>> @@ -554,6 +557,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu,
>> struct kvm_run *run)
>>                          kvm_vgic_sync_hwstate(vcpu);
>>                          preempt_enable();
>>                          kvm_timer_sync_hwstate(vcpu);
>> +                       kvm_pmu_sync_hwstate(vcpu);
>>                          continue;
>>                  }
>>
>> @@ -604,6 +608,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu,
>> struct kvm_run *run)
>>
>>                  kvm_timer_sync_hwstate(vcpu);
>>
>> +               kvm_pmu_sync_hwstate(vcpu);
>> +
>>                  ret = handle_exit(vcpu, run, ret);
>>          }
>
> yeah, that's more like it!
>
>>
>> diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
>> index 47bbd43..edfe4e5 100644
>> --- a/include/kvm/arm_pmu.h
>> +++ b/include/kvm/arm_pmu.h
>> @@ -41,6 +41,8 @@ struct kvm_pmu {
>>   };
>>
>>   #ifdef CONFIG_KVM_ARM_PMU
>> +void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
>> +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
>>   unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32
>> select_idx);
>>   void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
>>   void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool
>> all_enable);
>> @@ -51,6 +53,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu
>> *vcpu, u32 data,
>>                                      u32 select_idx);
>>   void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val);
>>   #else
>> +void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
>> +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
>>   unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32
>> select_idx)
>>   {
>>          return 0;
>> diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
>> index 15cac45..9aad2f7 100644
>> --- a/virt/kvm/arm/pmu.c
>> +++ b/virt/kvm/arm/pmu.c
>> @@ -21,6 +21,7 @@
>>   #include <linux/perf_event.h>
>>   #include <asm/kvm_emulate.h>
>>   #include <kvm/arm_pmu.h>
>> +#include <kvm/arm_vgic.h>
>>
>>   /**
>>    * kvm_pmu_get_counter_value - get PMU counter value
>> @@ -79,6 +80,78 @@ static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
>>   }
>>
>>   /**
>> + * kvm_pmu_flush_hwstate - flush pmu state to cpu
>> + * @vcpu: The vcpu pointer
>> + *
>> + * Inject virtual PMU IRQ if IRQ is pending for this cpu.
>> + */
>> +void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
>> +{
>> +       struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> +       u32 overflow;
>> +
>> +       if (!vcpu_mode_is_32bit(vcpu))
>> +               overflow = vcpu_sys_reg(vcpu, PMOVSSET_EL0);
>> +       else
>> +               overflow = vcpu_cp15(vcpu, c9_PMOVSSET);
>> +
>> +       if ((pmu->irq_pending || overflow != 0) && (pmu->irq_num != -1))
>> +               kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
>> pmu->irq_num, 1);
>> +
>> +       pmu->irq_pending = false;
>
> Now, we get to the critical point. Why do you need to keep this shadow
> state for the interrupt?
>
The reason is that when guest clear the overflow register, it will trap 
to kvm and call kvm_pmu_sync_hwstate() as you see above. At this moment, 
the overflow register is still overflowed(that is some bit is still 1). 
So We need to use some flag to mark we already inject this interrupt. 
And if during guest handling the overflow, there is a new overflow 
happening, the pmu->irq_pending will be set ture by 
kvm_pmu_perf_overflow(), then it needs to inject this new interrupt, right?

> The way I see it, you should set the line high when the overflow has
> been registered, and set it low when the overflow condition has been
> cleared by the guest. And nothing else.
>
>> +}
>> +
>> +/**
>> + * kvm_pmu_sync_hwstate - sync pmu state for cpu
>> + * @vcpu: The vcpu pointer
>> + *
>> + * Inject virtual PMU IRQ if IRQ is pending for this cpu when back from
>> guest.
>> + */
>> +void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu)
>> +{
>> +       struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> +
>> +       if (pmu->irq_pending && (pmu->irq_num != -1))
>> +               kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
>> pmu->irq_num, 1);
>> +
>> +       pmu->irq_pending = false;
>> +}
>>
>
> Why do you have to do it twice??
>
> Thanks,
>
> 	M.
>

-- 
Shannon

  reply	other threads:[~2015-12-01 15:13 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-30  6:21 [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-11-30 18:11   ` Marc Zyngier
2015-10-30  6:21 ` [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-11-02 20:06   ` Christopher Covington
2015-11-30 17:56   ` Marc Zyngier
2015-12-01  1:51     ` Shannon Zhao
2015-12-01  8:49       ` Marc Zyngier
2015-12-01 12:46         ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-11-30 11:42   ` Marc Zyngier
2015-11-30 11:59     ` Shannon Zhao
2015-11-30 13:19       ` Marc Zyngier
2015-10-30  6:21 ` [PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-11-02 20:13   ` Christopher Covington
2015-11-03  2:33     ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-11-02 20:54   ` Christopher Covington
2015-11-03  2:41     ` Shannon Zhao
2015-11-30 18:12   ` Marc Zyngier
2015-12-01  2:42     ` Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-10-30  6:21 ` [PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-11-02 21:20   ` Christopher Covington
2015-10-30  6:22 ` [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-10-30 12:08   ` kbuild test robot
2015-10-31  2:06     ` Shannon Zhao
2015-11-30 18:22   ` Marc Zyngier
2015-12-01 14:35     ` Shannon Zhao
2015-12-01 14:50       ` Marc Zyngier
2015-12-01 15:13         ` Shannon Zhao [this message]
2015-12-01 15:41           ` Marc Zyngier
2015-12-01 16:26             ` Shannon Zhao
2015-12-01 16:57               ` Marc Zyngier
2015-12-02  2:40                 ` Shannon Zhao
2015-12-02  8:45                   ` Marc Zyngier
2015-12-02  9:49                     ` Shannon Zhao
2015-12-02 10:22                       ` Marc Zyngier
2015-12-02 16:27                         ` Christoffer Dall
2015-10-30  6:22 ` [PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-10-30  6:22 ` [PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-10-30  6:22 ` [PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-11-30 18:31   ` Marc Zyngier
2015-11-30 18:34 ` [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-12-01  1:52   ` Shannon Zhao

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