* [PATCH v6 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
2015-12-05 11:53 [PATCH v6 0/5] SMP support for Broadcom NSP Kapil Hali
@ 2015-12-05 11:53 ` Kapil Hali
2015-12-07 3:49 ` Florian Fainelli
2015-12-07 14:16 ` Rob Herring
2015-12-05 11:53 ` [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona Kapil Hali
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Kapil Hali @ 2015-12-05 11:53 UTC (permalink / raw)
To: linux-arm-kernel
Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
.../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
2 files changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 0000000..677ef9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,39 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPU in the following Broadcom SoCs:
+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the corresponding secondary "cpu" device tree node:
+ - enable-method = "brcm,bcm-nsp-smp";
+ - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register which should hold the common
+entry point for a secondary CPU. This entry is cpu node specific
+and should be added per cpu. E.g., in case of NSP (BCM58625) which
+is a dual core CPU SoC, this entry should be added to cpu1 node.
+
+
+Example:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0xffff042c>;
+ reg = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 3a07a87..d191554 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,psci"
+ "brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
"marvell,armada-380-smp"
--
2.1.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v6 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
2015-12-05 11:53 ` [PATCH v6 1/5] dt-bindings: add SMP enable-method " Kapil Hali
@ 2015-12-07 3:49 ` Florian Fainelli
2015-12-07 14:16 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Florian Fainelli @ 2015-12-07 3:49 UTC (permalink / raw)
To: linux-arm-kernel
Le 05/12/2015 03:53, Kapil Hali a ?crit :
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Applied to devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 1/5] dt-bindings: add SMP enable-method for Broadcom NSP
2015-12-05 11:53 ` [PATCH v6 1/5] dt-bindings: add SMP enable-method " Kapil Hali
2015-12-07 3:49 ` Florian Fainelli
@ 2015-12-07 14:16 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2015-12-07 14:16 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 05, 2015 at 06:53:40AM -0500, Kapil Hali wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> 2 files changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..677ef9d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,39 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPU in the following Broadcom SoCs:
> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the corresponding secondary "cpu" device tree node:
> + - enable-method = "brcm,bcm-nsp-smp";
> + - secondary-boot-reg = <...>;
> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register which should hold the common
> +entry point for a secondary CPU. This entry is cpu node specific
> +and should be added per cpu. E.g., in case of NSP (BCM58625) which
> +is a dual core CPU SoC, this entry should be added to cpu1 node.
> +
> +
> +Example:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <0>;
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + enable-method = "brcm,bcm-nsp-smp";
> + secondary-boot-reg = <0xffff042c>;
> + reg = <1>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 3a07a87..d191554 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
> "allwinner,sun6i-a31"
> "allwinner,sun8i-a23"
> "arm,psci"
> + "brcm,bcm-nsp-smp"
> "brcm,brahma-b15"
> "marvell,armada-375-smp"
> "marvell,armada-380-smp"
> --
> 2.1.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
2015-12-05 11:53 [PATCH v6 0/5] SMP support for Broadcom NSP Kapil Hali
2015-12-05 11:53 ` [PATCH v6 1/5] dt-bindings: add SMP enable-method " Kapil Hali
@ 2015-12-05 11:53 ` Kapil Hali
2015-12-07 3:50 ` Florian Fainelli
2015-12-07 14:23 ` Rob Herring
2015-12-05 11:53 ` [PATCH v6 3/5] ARM: dts: Add SMP support for Broadcom NSP Kapil Hali
` (2 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Kapil Hali @ 2015-12-05 11:53 UTC (permalink / raw)
To: linux-arm-kernel
These changes cleans up SMP implementaion for Broadcom's
Kona SoC which are required for handling SMP for iProc
family of SoCs at a single place for BCM NSP and BCM Kona.
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
.../bindings/arm/bcm/brcm,bcm11351-cpu-method.txt | 12 ++--
arch/arm/boot/dts/bcm11351.dtsi | 4 +-
arch/arm/boot/dts/bcm21664.dtsi | 4 +-
arch/arm/mach-bcm/kona_smp.c | 82 ++++++++++++++--------
4 files changed, 64 insertions(+), 38 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
index 8240c02..3c5fe4b 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
@@ -1,17 +1,17 @@
Broadcom Kona Family CPU Enable Method
--------------------------------------
This binding defines the enable method used for starting secondary
-CPUs in the following Broadcom SoCs:
+CPU in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
The enable method is specified by defining the following required
-properties in the "cpus" device tree node:
+properties in the corresponding secondary "cpu" device tree node:
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
-physical address of the register used to request the ROM holding pen
-code release a secondary CPU. The value written to the register is
+physical address of the register used to request the ROM code
+release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
@@ -19,8 +19,6 @@ Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
cpu0: cpu at 0 {
device_type = "cpu";
@@ -31,6 +29,8 @@ Example:
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ enable-method = "brcm,bcm11351-cpu-method";
+ secondary-boot-reg = <0x3500417c>;
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 2ddaa51..18045c3 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -30,8 +30,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
cpu0: cpu at 0 {
device_type = "cpu";
@@ -42,6 +40,8 @@
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ enable-method = "brcm,bcm11351-cpu-method";
+ secondary-boot-reg = <0x3500417c>;
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 2016b72..6dde95f 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -30,8 +30,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x35004178>;
cpu0: cpu at 0 {
device_type = "cpu";
@@ -42,6 +40,8 @@
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ enable-method = "brcm,bcm11351-cpu-method";
+ secondary-boot-reg = <0x35004178>;
reg = <1>;
};
};
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c
index 66a0465..15af781 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/kona_smp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
* Copyright 2014 Linaro Limited
*
* This program is free software; you can redistribute it and/or
@@ -30,9 +30,10 @@
/* Name of device node property defining secondary boot register location */
#define OF_SECONDARY_BOOT "secondary-boot-reg"
+#define MPIDR_CPUID_BITMASK 0x3
/* I/O address of register used to coordinate secondary core startup */
-static u32 secondary_boot;
+static u32 secondary_boot_addr;
/*
* Enable the Cortex A9 Snoop Control Unit
@@ -78,44 +79,68 @@ static int __init scu_a9_enable(void)
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
- struct device_node *node;
+ struct device_node *cpus_node = NULL;
+ struct device_node *cpu_node = NULL;
int ret;
- BUG_ON(secondary_boot); /* We're called only once */
-
/*
* This function is only called via smp_ops->smp_prepare_cpu().
* That only happens if a "/cpus" device tree node exists
* and has an "enable-method" property that selects the SMP
* operations defined herein.
*/
- node = of_find_node_by_path("/cpus");
- BUG_ON(!node);
-
- /*
- * Our secondary enable method requires a "secondary-boot-reg"
- * property to specify a register address used to request the
- * ROM code boot a secondary code. If we have any trouble
- * getting this we fall back to uniprocessor mode.
- */
- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
- node->name);
- ret = -ENOENT; /* Arrange to disable SMP */
- goto out;
+ cpus_node = of_find_node_by_path("/cpus");
+ if (!cpus_node)
+ return;
+
+ for_each_child_of_node(cpus_node, cpu_node) {
+ u32 cpuid;
+
+ if (of_node_cmp(cpu_node->type, "cpu"))
+ continue;
+
+ if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
+ pr_debug("%s: missing reg property\n",
+ cpu_node->full_name);
+ ret = -ENOENT;
+ goto out;
+ }
+
+ /*
+ * "secondary-boot-reg" property should be defined only
+ * for secondary cpu
+ */
+ if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
+ /*
+ * Our secondary enable method requires a
+ * "secondary-boot-reg" property to specify a register
+ * address used to request the ROM code boot a secondary
+ * core. If we have any trouble getting this we fall
+ * back to uniprocessor mode.
+ */
+ if (of_property_read_u32(cpu_node,
+ OF_SECONDARY_BOOT,
+ &secondary_boot_addr)) {
+ pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
+ cpu_node->name);
+ ret = -ENOENT;
+ goto out;
+ }
+ }
}
/*
- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
+ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
* returned, the SoC reported a uniprocessor configuration.
* We bail on any other error.
*/
ret = scu_a9_enable();
out:
- of_node_put(node);
+ of_node_put(cpu_node);
+ of_node_put(cpus_node);
+
if (ret) {
/* Update the CPU present map to reflect uniprocessor mode */
- BUG_ON(ret != -ENOENT);
pr_warn("disabling SMP\n");
init_cpu_present(&only_cpu_0);
}
@@ -139,7 +164,7 @@ out:
* - Wait for the secondary boot register to be re-written, which
* indicates the secondary core has started.
*/
-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
void __iomem *boot_reg;
phys_addr_t boot_func;
@@ -154,15 +179,16 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -EINVAL;
}
- if (!secondary_boot) {
+ if (!secondary_boot_addr) {
pr_err("required secondary boot register not specified\n");
return -EINVAL;
}
- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
+ boot_reg = ioremap_nocache(
+ (phys_addr_t)secondary_boot_addr, sizeof(u32));
if (!boot_reg) {
pr_err("unable to map boot register for cpu %u\n", cpu_id);
- return -ENOSYS;
+ return -ENOMEM;
}
/*
@@ -191,12 +217,12 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
pr_err("timeout waiting for cpu %u to start\n", cpu_id);
- return -ENOSYS;
+ return -ENXIO;
}
static struct smp_operations bcm_smp_ops __initdata = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
- .smp_boot_secondary = bcm_boot_secondary,
+ .smp_boot_secondary = kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
&bcm_smp_ops);
--
2.1.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
2015-12-05 11:53 ` [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona Kapil Hali
@ 2015-12-07 3:50 ` Florian Fainelli
2015-12-07 14:23 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Florian Fainelli @ 2015-12-07 3:50 UTC (permalink / raw)
To: linux-arm-kernel
Le 05/12/2015 03:53, Kapil Hali a ?crit :
> These changes cleans up SMP implementaion for Broadcom's
> Kona SoC which are required for handling SMP for iProc
> family of SoCs at a single place for BCM NSP and BCM Kona.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Applied to soc/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona
2015-12-05 11:53 ` [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona Kapil Hali
2015-12-07 3:50 ` Florian Fainelli
@ 2015-12-07 14:23 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2015-12-07 14:23 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 05, 2015 at 06:53:41AM -0500, Kapil Hali wrote:
> These changes cleans up SMP implementaion for Broadcom's
> Kona SoC which are required for handling SMP for iProc
> family of SoCs at a single place for BCM NSP and BCM Kona.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
> ---
> .../bindings/arm/bcm/brcm,bcm11351-cpu-method.txt | 12 ++--
> arch/arm/boot/dts/bcm11351.dtsi | 4 +-
> arch/arm/boot/dts/bcm21664.dtsi | 4 +-
For the bindings:
Acked-by: Rob Herring <robh@kernel.org>
> arch/arm/mach-bcm/kona_smp.c | 82 ++++++++++++++--------
> 4 files changed, 64 insertions(+), 38 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
> index 8240c02..3c5fe4b 100644
> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
> @@ -1,17 +1,17 @@
> Broadcom Kona Family CPU Enable Method
> --------------------------------------
> This binding defines the enable method used for starting secondary
> -CPUs in the following Broadcom SoCs:
> +CPU in the following Broadcom SoCs:
> BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
>
> The enable method is specified by defining the following required
> -properties in the "cpus" device tree node:
> +properties in the corresponding secondary "cpu" device tree node:
> - enable-method = "brcm,bcm11351-cpu-method";
> - secondary-boot-reg = <...>;
>
> The secondary-boot-reg property is a u32 value that specifies the
> -physical address of the register used to request the ROM holding pen
> -code release a secondary CPU. The value written to the register is
> +physical address of the register used to request the ROM code
> +release a secondary CPU. The value written to the register is
> formed by encoding the target CPU id into the low bits of the
> physical start address it should jump to.
>
> @@ -19,8 +19,6 @@ Example:
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> - enable-method = "brcm,bcm11351-cpu-method";
> - secondary-boot-reg = <0x3500417c>;
>
> cpu0: cpu at 0 {
> device_type = "cpu";
> @@ -31,6 +29,8 @@ Example:
> cpu1: cpu at 1 {
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> + enable-method = "brcm,bcm11351-cpu-method";
> + secondary-boot-reg = <0x3500417c>;
> reg = <1>;
> };
> };
> diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
> index 2ddaa51..18045c3 100644
> --- a/arch/arm/boot/dts/bcm11351.dtsi
> +++ b/arch/arm/boot/dts/bcm11351.dtsi
> @@ -30,8 +30,6 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> - enable-method = "brcm,bcm11351-cpu-method";
> - secondary-boot-reg = <0x3500417c>;
>
> cpu0: cpu at 0 {
> device_type = "cpu";
> @@ -42,6 +40,8 @@
> cpu1: cpu at 1 {
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> + enable-method = "brcm,bcm11351-cpu-method";
> + secondary-boot-reg = <0x3500417c>;
> reg = <1>;
> };
> };
> diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
> index 2016b72..6dde95f 100644
> --- a/arch/arm/boot/dts/bcm21664.dtsi
> +++ b/arch/arm/boot/dts/bcm21664.dtsi
> @@ -30,8 +30,6 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> - enable-method = "brcm,bcm11351-cpu-method";
> - secondary-boot-reg = <0x35004178>;
>
> cpu0: cpu at 0 {
> device_type = "cpu";
> @@ -42,6 +40,8 @@
> cpu1: cpu at 1 {
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> + enable-method = "brcm,bcm11351-cpu-method";
> + secondary-boot-reg = <0x35004178>;
> reg = <1>;
> };
> };
> diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c
> index 66a0465..15af781 100644
> --- a/arch/arm/mach-bcm/kona_smp.c
> +++ b/arch/arm/mach-bcm/kona_smp.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2014 Broadcom Corporation
> + * Copyright (C) 2014-2015 Broadcom Corporation
> * Copyright 2014 Linaro Limited
> *
> * This program is free software; you can redistribute it and/or
> @@ -30,9 +30,10 @@
>
> /* Name of device node property defining secondary boot register location */
> #define OF_SECONDARY_BOOT "secondary-boot-reg"
> +#define MPIDR_CPUID_BITMASK 0x3
>
> /* I/O address of register used to coordinate secondary core startup */
> -static u32 secondary_boot;
> +static u32 secondary_boot_addr;
>
> /*
> * Enable the Cortex A9 Snoop Control Unit
> @@ -78,44 +79,68 @@ static int __init scu_a9_enable(void)
> static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
> {
> static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
> - struct device_node *node;
> + struct device_node *cpus_node = NULL;
> + struct device_node *cpu_node = NULL;
> int ret;
>
> - BUG_ON(secondary_boot); /* We're called only once */
> -
> /*
> * This function is only called via smp_ops->smp_prepare_cpu().
> * That only happens if a "/cpus" device tree node exists
> * and has an "enable-method" property that selects the SMP
> * operations defined herein.
> */
> - node = of_find_node_by_path("/cpus");
> - BUG_ON(!node);
> -
> - /*
> - * Our secondary enable method requires a "secondary-boot-reg"
> - * property to specify a register address used to request the
> - * ROM code boot a secondary code. If we have any trouble
> - * getting this we fall back to uniprocessor mode.
> - */
> - if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
> - pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
> - node->name);
> - ret = -ENOENT; /* Arrange to disable SMP */
> - goto out;
> + cpus_node = of_find_node_by_path("/cpus");
> + if (!cpus_node)
> + return;
> +
> + for_each_child_of_node(cpus_node, cpu_node) {
> + u32 cpuid;
> +
> + if (of_node_cmp(cpu_node->type, "cpu"))
> + continue;
> +
> + if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
> + pr_debug("%s: missing reg property\n",
> + cpu_node->full_name);
> + ret = -ENOENT;
> + goto out;
> + }
> +
> + /*
> + * "secondary-boot-reg" property should be defined only
> + * for secondary cpu
> + */
> + if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
> + /*
> + * Our secondary enable method requires a
> + * "secondary-boot-reg" property to specify a register
> + * address used to request the ROM code boot a secondary
> + * core. If we have any trouble getting this we fall
> + * back to uniprocessor mode.
> + */
> + if (of_property_read_u32(cpu_node,
> + OF_SECONDARY_BOOT,
> + &secondary_boot_addr)) {
> + pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
> + cpu_node->name);
> + ret = -ENOENT;
> + goto out;
> + }
> + }
> }
>
> /*
> - * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
> + * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
> * returned, the SoC reported a uniprocessor configuration.
> * We bail on any other error.
> */
> ret = scu_a9_enable();
> out:
> - of_node_put(node);
> + of_node_put(cpu_node);
> + of_node_put(cpus_node);
> +
> if (ret) {
> /* Update the CPU present map to reflect uniprocessor mode */
> - BUG_ON(ret != -ENOENT);
> pr_warn("disabling SMP\n");
> init_cpu_present(&only_cpu_0);
> }
> @@ -139,7 +164,7 @@ out:
> * - Wait for the secondary boot register to be re-written, which
> * indicates the secondary core has started.
> */
> -static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> void __iomem *boot_reg;
> phys_addr_t boot_func;
> @@ -154,15 +179,16 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
> return -EINVAL;
> }
>
> - if (!secondary_boot) {
> + if (!secondary_boot_addr) {
> pr_err("required secondary boot register not specified\n");
> return -EINVAL;
> }
>
> - boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
> + boot_reg = ioremap_nocache(
> + (phys_addr_t)secondary_boot_addr, sizeof(u32));
> if (!boot_reg) {
> pr_err("unable to map boot register for cpu %u\n", cpu_id);
> - return -ENOSYS;
> + return -ENOMEM;
> }
>
> /*
> @@ -191,12 +217,12 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> pr_err("timeout waiting for cpu %u to start\n", cpu_id);
>
> - return -ENOSYS;
> + return -ENXIO;
> }
>
> static struct smp_operations bcm_smp_ops __initdata = {
> .smp_prepare_cpus = bcm_smp_prepare_cpus,
> - .smp_boot_secondary = bcm_boot_secondary,
> + .smp_boot_secondary = kona_boot_secondary,
> };
> CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
> &bcm_smp_ops);
> --
> 2.1.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 3/5] ARM: dts: Add SMP support for Broadcom NSP
2015-12-05 11:53 [PATCH v6 0/5] SMP support for Broadcom NSP Kapil Hali
2015-12-05 11:53 ` [PATCH v6 1/5] dt-bindings: add SMP enable-method " Kapil Hali
2015-12-05 11:53 ` [PATCH v6 2/5] ARM: BCM: Clean up SMP support for Broadcom Kona Kapil Hali
@ 2015-12-05 11:53 ` Kapil Hali
2015-12-07 3:50 ` Florian Fainelli
2015-12-05 11:53 ` [PATCH v6 4/5] ARM: BCM: " Kapil Hali
2015-12-05 11:53 ` [PATCH v6 5/5] ARM: BCM: Add SMP support for Broadcom 4708 Kapil Hali
4 siblings, 1 reply; 13+ messages in thread
From: Kapil Hali @ 2015-12-05 11:53 UTC (permalink / raw)
To: linux-arm-kernel
Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++++++++++++++++++++------------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..d9f8b31 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0x0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0xffff042c>;
+ reg = <0x1>;
+ };
+ };
+
mpcore {
compatible = "simple-bus";
ranges = <0x00000000 0x19020000 0x00003000>;
#address-cells = <1>;
#size-cells = <1>;
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
- reg = <0x0>;
- };
- };
-
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x2000 0x1000>;
--
2.1.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v6 4/5] ARM: BCM: Add SMP support for Broadcom NSP
2015-12-05 11:53 [PATCH v6 0/5] SMP support for Broadcom NSP Kapil Hali
` (2 preceding siblings ...)
2015-12-05 11:53 ` [PATCH v6 3/5] ARM: dts: Add SMP support for Broadcom NSP Kapil Hali
@ 2015-12-05 11:53 ` Kapil Hali
2015-12-07 3:50 ` Florian Fainelli
2015-12-05 11:53 ` [PATCH v6 5/5] ARM: BCM: Add SMP support for Broadcom 4708 Kapil Hali
4 siblings, 1 reply; 13+ messages in thread
From: Kapil Hali @ 2015-12-05 11:53 UTC (permalink / raw)
To: linux-arm-kernel
Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP handling in a common file.
Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
arch/arm/mach-bcm/Kconfig | 2 +
arch/arm/mach-bcm/Makefile | 8 +++-
arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 64 ++++++++++++++++++++++++++++-
3 files changed, 71 insertions(+), 3 deletions(-)
rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (81%)
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 8c53c55..83765a0 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_BCM_NSP
select ARCH_BCM_IPROC
select ARM_ERRATA_754322
select ARM_ERRATA_775420
+ select ARM_ERRATA_764369 if SMP
+ select HAVE_SMP
help
Support for Broadcom Northstar Plus SoC.
Broadcom Northstar Plus family of SoCs are used for switching control
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..5193a25 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,7 +14,11 @@
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
# Northstar Plus
-obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+
+ifeq ($(CONFIG_ARCH_BCM_NSP),y)
+obj-$(CONFIG_SMP) += platsmp.o
+endif
# BCM281XX
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
@@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
# BCM281XX and BCM21664 SMP support
-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
# BCM281XX and BCM21664 L2 cache control
obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
similarity index 81%
rename from arch/arm/mach-bcm/kona_smp.c
rename to arch/arm/mach-bcm/platsmp.c
index 15af781..ea4201e 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -12,12 +12,17 @@
* GNU General Public License for more details.
*/
-#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
#include <linux/errno.h>
+#include <linux/init.h>
#include <linux/io.h>
+#include <linux/jiffies.h>
#include <linux/of.h>
#include <linux/sched.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
#include <asm/smp.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
@@ -76,6 +81,36 @@ static int __init scu_a9_enable(void)
return 0;
}
+static int nsp_write_lut(void)
+{
+ void __iomem *sku_rom_lut;
+ phys_addr_t secondary_startup_phy;
+
+ if (!secondary_boot_addr) {
+ pr_warn("required secondary boot register not specified\n");
+ return -EINVAL;
+ }
+
+ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
+ sizeof(secondary_boot_addr));
+ if (!sku_rom_lut) {
+ pr_warn("unable to ioremap SKU-ROM LUT register\n");
+ return -ENOMEM;
+ }
+
+ secondary_startup_phy = virt_to_phys(secondary_startup);
+ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
+
+ writel_relaxed(secondary_startup_phy, sku_rom_lut);
+
+ /* Ensure the write is visible to the secondary core */
+ smp_wmb();
+
+ iounmap(sku_rom_lut);
+
+ return 0;
+}
+
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
@@ -220,9 +255,36 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -ENXIO;
}
+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int ret;
+
+ /*
+ * After wake up, secondary core branches to the startup
+ * address programmed at SKU ROM LUT location.
+ */
+ ret = nsp_write_lut();
+ if (ret) {
+ pr_err("unable to write startup addr to SKU ROM LUT\n");
+ goto out;
+ }
+
+ /* Send a CPU wakeup interrupt to the secondary core */
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+out:
+ return ret;
+}
+
static struct smp_operations bcm_smp_ops __initdata = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
.smp_boot_secondary = kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
&bcm_smp_ops);
+
+struct smp_operations nsp_smp_ops __initdata = {
+ .smp_prepare_cpus = bcm_smp_prepare_cpus,
+ .smp_boot_secondary = nsp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
--
2.1.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v6 4/5] ARM: BCM: Add SMP support for Broadcom NSP
2015-12-05 11:53 ` [PATCH v6 4/5] ARM: BCM: " Kapil Hali
@ 2015-12-07 3:50 ` Florian Fainelli
0 siblings, 0 replies; 13+ messages in thread
From: Florian Fainelli @ 2015-12-07 3:50 UTC (permalink / raw)
To: linux-arm-kernel
Le 05/12/2015 03:53, Kapil Hali a ?crit :
> Add SMP support for Broadcom's Northstar Plus SoC
> cpu enable method. This changes also consolidates
> iProc family's - BCM NSP and BCM Kona, platform
> SMP handling in a common file.
>
> Northstar Plus SoC is based on ARM Cortex-A9
> revision r3p0 which requires configuration for ARM
> Errata 764369 for SMP. This change adds the needed
> configuration option.
>
> Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Applied to soc/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 5/5] ARM: BCM: Add SMP support for Broadcom 4708
2015-12-05 11:53 [PATCH v6 0/5] SMP support for Broadcom NSP Kapil Hali
` (3 preceding siblings ...)
2015-12-05 11:53 ` [PATCH v6 4/5] ARM: BCM: " Kapil Hali
@ 2015-12-05 11:53 ` Kapil Hali
2015-12-07 3:51 ` Florian Fainelli
4 siblings, 1 reply; 13+ messages in thread
From: Kapil Hali @ 2015-12-05 11:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Jon Mason <jonmason@broadcom.com>
Add SMP support for Broadcom's 4708 SoCs.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
---
arch/arm/boot/dts/bcm4708.dtsi | 3 ++-
arch/arm/mach-bcm/Kconfig | 1 +
arch/arm/mach-bcm/Makefile | 3 +++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..f2d2239 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -27,8 +27,9 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
+ enable-method = "brcm,bcm-nsp-smp";
+ secondary-boot-reg = <0xffff0400>;
reg = <0x1>;
};
};
-
};
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 83765a0..e85246f 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
config ARCH_BCM_5301X
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
select ARCH_BCM_IPROC
+ select HAVE_SMP
help
Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 5193a25..7d66515 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
# BCM5301X
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP) += platsmp.o
+endif
# BCM63XXx
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
--
2.1.0
^ permalink raw reply related [flat|nested] 13+ messages in thread