From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register
Date: Mon, 07 Dec 2015 13:38:02 +0000 [thread overview]
Message-ID: <56658BBA.4040600@arm.com> (raw)
In-Reply-To: <1449123091-20252-9-git-send-email-zhaoshenglong@huawei.com>
On 03/12/15 06:11, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or
> reset_unknown_cp15 for its reset handler. Add access handler which
> emulates writing and reading PMXEVTYPER register. When writing to
> PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event
> for the selected event type.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> arch/arm64/kvm/sys_regs.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index b0a8d88..6967a49 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -473,6 +473,17 @@ static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> vcpu_sys_reg(vcpu, r->reg) = pmceid;
> }
>
> +static bool pmu_counter_idx_valid(u64 pmcr, u64 idx)
> +{
> + u64 val;
> +
> + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
> + if (idx >= val && idx != ARMV8_COUNTER_MASK)
> + return false;
> +
> + return true;
> +}
> +
> /* PMU registers accessor. */
> static bool access_pmu_regs(struct kvm_vcpu *vcpu,
> const struct sys_reg_params *p,
> @@ -482,6 +493,20 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
>
> if (p->is_write) {
> switch (r->reg) {
> + case PMXEVTYPER_EL0: {
> + u64 idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
> + & ARMV8_COUNTER_MASK;
> +
> + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, PMCR_EL0),
> + idx))
> + break;
> +
> + val = *vcpu_reg(vcpu, p->Rt);
> + kvm_pmu_set_counter_event_type(vcpu, val, idx);
> + vcpu_sys_reg(vcpu, PMXEVTYPER_EL0) = val;
> + vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + idx) = val;
I'm really confused by this. PMXEVTYPER is not really a register, but
level of indirection between PMEVTYPERn_EL0 and PMCCFILTER_EL0
(depending on PMSELR_EL0.SEL). On its own, it doesn't exist.
Here, you are making PMXEVTYPER_EL0 an actual register, storing the same
value twice (and not handling PMCCFILTER_EL0). It definitely feels
wrong. You should be able to trap it and propagate the access to the
right register, without duplicating the state.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2015-12-07 13:38 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-03 6:11 [PATCH v5 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-12-07 15:05 ` Marc Zyngier
2015-12-07 16:42 ` Marc Zyngier
2015-12-03 6:11 ` [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-12-07 14:06 ` Marc Zyngier
2015-12-07 14:31 ` Shannon Zhao
2015-12-07 14:55 ` Marc Zyngier
2015-12-08 8:09 ` Shannon Zhao
2015-12-08 9:02 ` Marc Zyngier
2015-12-03 6:11 ` [PATCH v5 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-12-07 13:28 ` Marc Zyngier
2015-12-03 6:11 ` [PATCH v5 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-12-07 13:38 ` Marc Zyngier [this message]
2015-12-03 6:11 ` [PATCH v5 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-12-07 13:42 ` Marc Zyngier
2015-12-03 6:11 ` [PATCH v5 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-12-03 6:11 ` [PATCH v5 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-12-07 13:56 ` Marc Zyngier
2015-12-07 14:37 ` Shannon Zhao
2015-12-07 15:06 ` Marc Zyngier
2015-12-07 14:11 ` [PATCH v5 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-12-07 14:47 ` Shannon Zhao
2015-12-07 15:09 ` Marc Zyngier
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