From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 00/19] KVM: ARM64: Add guest PMU support
Date: Tue, 15 Dec 2015 15:41:54 +0000 [thread overview]
Message-ID: <567034C2.8090307@arm.com> (raw)
In-Reply-To: <1450169379-12336-1-git-send-email-zhaoshenglong@huawei.com>
On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> This patchset adds guest PMU support for KVM on ARM64. It takes
> trap-and-emulate approach. When guest wants to monitor one event, it
> will be trapped by KVM and KVM will call perf_event API to create a perf
> event and call relevant perf_event APIs to get the count value of event.
>
> Use perf to test this patchset in guest. When using "perf list", it
> shows the list of the hardware events and hardware cache events perf
> supports. Then use "perf stat -e EVENT" to monitor some event. For
> example, use "perf stat -e cycles" to count cpu cycles and
> "perf stat -e cache-misses" to count cache misses.
>
> Below are the outputs of "perf stat -r 5 sleep 5" when running in host
> and guest.
>
> Host:
> Performance counter stats for 'sleep 5' (5 runs):
>
> 0.549456 task-clock (msec) # 0.000 CPUs utilized ( +- 5.68% )
> 1 context-switches # 0.002 M/sec
> 0 cpu-migrations # 0.000 K/sec
> 48 page-faults # 0.088 M/sec ( +- 1.40% )
> 1146243 cycles # 2.086 GHz ( +- 5.71% )
> <not supported> stalled-cycles-frontend
> <not supported> stalled-cycles-backend
> 627195 instructions # 0.55 insns per cycle ( +- 15.65% )
> <not supported> branches
> 9826 branch-misses # 17.883 M/sec ( +- 1.10% )
>
> 5.000875516 seconds time elapsed ( +- 0.00% )
>
>
> Guest:
> Performance counter stats for 'sleep 5' (5 runs):
>
> 0.640712 task-clock (msec) # 0.000 CPUs utilized ( +- 0.41% )
> 1 context-switches # 0.002 M/sec
> 0 cpu-migrations # 0.000 K/sec
> 50 page-faults # 0.077 M/sec ( +- 1.37% )
> 1320428 cycles # 2.061 GHz ( +- 0.29% )
> <not supported> stalled-cycles-frontend
> <not supported> stalled-cycles-backend
> 642373 instructions # 0.49 insns per cycle ( +- 0.46% )
> <not supported> branches
> 10399 branch-misses # 16.230 M/sec ( +- 1.57% )
>
> 5.001181020 seconds time elapsed ( +- 0.00% )
>
>
> Have a cycle counter read test like below in guest and host:
>
> static void test(void)
> {
> unsigned long count, count1, count2;
> count1 = read_cycles();
> count++;
> count2 = read_cycles();
> }
>
> Host:
> count1: 3049567104
> count2: 3049567247
> delta: 143
>
> Guest:
> count1: 5281420890
> count2: 5281421068
> delta: 178
>
> The gap between guest and host is very small. One reason for this I
> think is that it doesn't count the cycles in EL2 and host since we add
> exclude_hv = 1. So the cycles spent to store/restore registers which
> happens at EL2 are not included.
>
> This patchset can be fetched from [1] and the relevant QEMU version for
> test can be fetched from [2].
>
> The results of 'perf test' can be found from [3][4].
> The results of perf_event_tests test suite can be found from [5][6].
>
> Also, I have tested "perf top" in two VMs and host at the same time. It
> works well.
So while things are steadily improving, there is still more things to do
(and the more I review the code, the more I find things, which worries me).
The biggest issue at the moment is the handling of accesses at EL0,
which should be forwarded to EL1 instead of ignoring the access when
denied. There is also the UNDEFINED accesses (which are pretty easy to
solve), and a couple of straightforward bugs and other nits that should
be easy to fix.
If you can fix the above and that the result looks good, I'll try to put
it into -next. But at the moment, it looks like we're not really on
track to make it into 4.5.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
prev parent reply other threads:[~2015-12-15 15:41 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-15 8:49 [PATCH v7 00/19] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-12-15 11:34 ` Marc Zyngier
2015-12-15 11:44 ` Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 02/19] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 03/19] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 04/19] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 06/19] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2015-12-15 14:20 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-12-17 15:22 ` Mark Rutland
2015-12-17 15:30 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register Shannon Zhao
2015-12-15 13:43 ` Marc Zyngier
2015-12-15 14:26 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2015-12-15 13:44 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-12-15 13:56 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-12-15 14:02 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-12-15 14:06 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2015-12-15 14:36 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 14/19] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2015-12-15 14:58 ` Marc Zyngier
2015-12-15 15:59 ` Shannon Zhao
2015-12-15 16:02 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 16/19] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-12-15 15:19 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 17/19] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 18/19] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-12-15 15:33 ` Marc Zyngier
2015-12-15 15:50 ` Shannon Zhao
2015-12-15 15:59 ` Marc Zyngier
2015-12-15 17:50 ` Andrew Jones
2015-12-15 20:47 ` Christoffer Dall
2015-12-16 7:31 ` Shannon Zhao
2015-12-16 8:06 ` Shannon Zhao
2015-12-16 9:04 ` Marc Zyngier
2015-12-16 9:29 ` Shannon Zhao
2015-12-16 20:33 ` Christoffer Dall
2015-12-17 7:22 ` Shannon Zhao
2015-12-17 8:33 ` Marc Zyngier
2015-12-17 8:41 ` Shannon Zhao
2015-12-17 9:38 ` Marc Zyngier
2015-12-17 10:10 ` Shannon Zhao
2015-12-17 10:38 ` Marc Zyngier
2015-12-18 10:00 ` Christoffer Dall
2015-12-15 15:41 ` Marc Zyngier [this message]
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