From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B47F9C10F0E for ; Fri, 12 Apr 2019 12:16:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85BF92077C for ; Fri, 12 Apr 2019 12:16:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZZ4IXiUh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85BF92077C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X0FFNkP9X8N6CLkCy5gDJPGVqTxaVuBn7F20oU+l7io=; b=ZZ4IXiUhUHKU7k O2RPcS+YTngMf6mHiTFdjlgi7zLeZ5unPB7gvucG0YIe6Q5qd5MNlMN4IoAUDJrvsjhc9a5H/fvhQ 8V1lZnMH25wUil7nRfEJCX7EWFVL5EzjcoMEhsMe1h3zhpHNSw5AGlzUo5UZrJBAdZO2tbVd97upx SZSEIsaHt8pwrVvYQSVP+TLIDRe50ZNlzKU6NplV37OO38leO4eRNW1kWBM4ngtGAq07sLCKVDQue rsx+qie1sFpwnoIRaJHagg7k1a/Ktv/kKkf9IYrKC0nXAswYrj0G38oEQ6reFVTp86HMalzMB2EuC 4tDhokeR2YUB+Qgi7bNA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEv68-0004WR-JU; Fri, 12 Apr 2019 12:16:00 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEv65-0004W4-8w; Fri, 12 Apr 2019 12:15:58 +0000 Received: from ip5f5a6320.dynamic.kabel-deutschland.de ([95.90.99.32] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1hEv63-0005RQ-9J; Fri, 12 Apr 2019 14:15:55 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Elaine Zhang Subject: Re: [PATCH v1 5/6] clk: rockchip: add pll up and down when change pll freq Date: Fri, 12 Apr 2019 14:15:54 +0200 Message-ID: <5677286.2uEqRd8HI1@diego> In-Reply-To: <1554284649-26764-1-git-send-email-zhangqing@rock-chips.com> References: <1554284549-24916-1-git-send-email-zhangqing@rock-chips.com> <1554284649-26764-1-git-send-email-zhangqing@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190412_051557_456071_BD3979EF X-CRM114-Status: GOOD ( 17.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com, sboyd@kernel.org, mturquette@baylibre.com, briannorris@chromium.org, linux-kernel@vger.kernel.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Elaine, Am Mittwoch, 3. April 2019, 11:44:09 CEST schrieb Elaine Zhang: > set pll sequence: > ->set pll to slow mode or other plls > ->set pll down > ->set pll params > ->set pll up > ->wait pll lock status > ->set pll to normal mode > > To slove the system error: > wait_pll_lock: timeout waiting for pll to lock > pll_set_params: pll update unsucessful, > trying to restore old params Can you tell me on what soc this was experienced? The patch includes rk3399, but I don't think the CrOS kernel does powerdown the pll when changing the cpu-frequency [added Doug and Brian for clarification and possible testing :-) ] But I did find that the M0 code in ATF does actually power-down the PLL and follow your outline from above. So essentially I'd just like a thumbs up from chromeos people if they have the time. Heiko > Signed-off-by: Elaine Zhang > --- > drivers/clk/rockchip/clk-pll.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c > index dd0433d4753e..9fe1227e77e9 100644 > --- a/drivers/clk/rockchip/clk-pll.c > +++ b/drivers/clk/rockchip/clk-pll.c > @@ -208,6 +208,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, > rate_change_remuxed = 1; > } > > + /* set pll power down */ > + writel(HIWORD_UPDATE(1, > + RK3036_PLLCON1_PWRDOWN, 13), > + pll->reg_base + RK3036_PLLCON(1)); > + > /* update pll values */ > writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, > RK3036_PLLCON0_FBDIV_SHIFT) | > @@ -229,6 +234,10 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, > pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; > writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); > > + /* set pll power up */ > + writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 13), > + pll->reg_base + RK3036_PLLCON(1)); > + > /* wait for the pll to lock */ > ret = rockchip_pll_wait_lock(pll); > if (ret) { > @@ -685,6 +694,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, > rate_change_remuxed = 1; > } > > + /* set pll power down */ > + writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, > + RK3399_PLLCON3_PWRDOWN, 0), > + pll->reg_base + RK3399_PLLCON(3)); > + > /* update pll values */ > writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, > RK3399_PLLCON0_FBDIV_SHIFT), > @@ -708,6 +722,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, > RK3399_PLLCON3_DSMPD_SHIFT), > pll->reg_base + RK3399_PLLCON(3)); > > + /* set pll power up */ > + writel(HIWORD_UPDATE(0, > + RK3399_PLLCON3_PWRDOWN, 0), > + pll->reg_base + RK3399_PLLCON(3)); > + > /* wait for the pll to lock */ > ret = rockchip_rk3399_pll_wait_lock(pll); > if (ret) { > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel