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Thu, 05 Dec 2024 14:45:36 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 94F6240047; Thu, 5 Dec 2024 14:44:15 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9A014264FCA; Thu, 5 Dec 2024 14:41:27 +0100 (CET) Received: from [10.129.178.212] (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 5 Dec 2024 14:41:26 +0100 Message-ID: <569904ad-2b70-4a58-98fe-4f24e1089e17@foss.st.com> Date: Thu, 5 Dec 2024 14:41:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings To: Bjorn Helgaas , Rob Herring CC: , , , , , , , , , , , , , , , , References: <20241203222515.GA2967814@bhelgaas> Content-Language: en-US From: Christian Bruel In-Reply-To: <20241203222515.GA2967814@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.129.178.212] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241205_054553_939191_F54431F1 X-CRM114-Status: GOOD ( 17.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/3/24 23:25, Bjorn Helgaas wrote: > On Tue, Nov 26, 2024 at 04:51:15PM +0100, Christian Bruel wrote: >> Document the bindings for STM32MP25 PCIe Controller configured in >> root complex mode. >> >> Supports 4 legacy interrupts and MSI interrupts from the ARM >> GICv2m controller. > > s/legacy/INTx/ > >> STM32 PCIe may be in a power domain which is the case for the STM32MP25 >> based boards. >> >> Supports wake# from wake-gpios > > s/wake#/WAKE#/ > >> + wake-gpios: >> + description: GPIO controlled connection to WAKE# input signal > > I'm not a hardware guy, but this sounds like a GPIO that *reads* > WAKE#, not controls it. Rephrasing as "GPIO used as WAKE# input signal" (output for the endpoint bindings) > >> + pcie@48400000 { >> + compatible = "st,stm32mp25-pcie-rc"; >> + device_type = "pci"; >> + num-lanes = <1>; > > num-lanes applies to a Root Port, not to a Root Complex. I know most > bindings conflate Root Ports with the Root Complex, maybe because many > of these controllers only support a single Root Port? > > But are we ever going to separate these out? I assume someday > controllers will support multiple Root Ports and/or additional devices > on the root bus, like RCiEPs, RCECs, etc., and we'll need per-RP phys, > max-link-speed, num-lanes, reset-gpios, etc. > > Seems like it would be to our benefit to split out the Root Ports when > we can, even if the current hardware only supports one, so we can > start untangling the code and data structures. OK. and we support only 1 lane anyway, so drop it. thanks, > > Bjorn