[PATCH v3 1/2] clk: sunxi: factors: Add missing recalc pointer copy

[PATCH v3 1/2] clk: sunxi: factors: Add missing recalc pointer copy

[Maxime Ripard]

Commit 4a9b2abc213e ("clk: sunxi: factors: Support custom formulas") was
introducing a custom recalc function. However, the pointer was never
filled, which was making the whole thing unused.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi/clk-factors.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index e480a6bcf1f6..6e97f46c0c37 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -212,6 +212,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
 	factors->reg = reg;
 	factors->config = data->table;
 	factors->get_factors = data->getter;
+	factors->recalc = data->recalc;
 	factors->lock = lock;
 
 	/* Add a gate if this factor clock can be gated */
-- 
2.6.4

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Maxime Ripard]

Remove the fixed dividers from the PLL6 driver to be able to have a
reusable driver that can be used across several SoCs that share the same
controller, but don't have the same set of dividers for this clock, and to
also be reused multiple times in the same SoC, since we're droping the
clock name.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
Changes from v2
  - Rebased and converted over to the new factors refactoring. Fixed the
    retrieved rate

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b6ad7850fac6..05fe3d1aa328 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -65,7 +65,7 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
-			clocks = <&pll6 0>;
+			clocks = <&pll6>;
 			status = "disabled";
 		};
 
@@ -73,7 +73,7 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&pll6 0>;
+			clocks = <&pll6>;
 			status = "disabled";
 		};
 	};
@@ -201,11 +201,11 @@
 		};
 
 		pll6: clk at 01c20028 {
-			#clock-cells = <1>;
+			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll6", "pll6x2";
+			clock-output-names = "pll6";
 		};
 
 		cpu: cpu at 01c20050 {
@@ -235,7 +235,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 			clock-output-names = "ahb1";
 
 			/*
@@ -244,7 +244,7 @@
 			 * controller requires AHB1 clocked from PLL6.
 			 */
 			assigned-clocks = <&ahb1>;
-			assigned-clock-parents = <&pll6 0>;
+			assigned-clock-parents = <&pll6>;
 		};
 
 		ahb1_gates: clk at 01c20060 {
@@ -307,7 +307,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-apb1-clk";
 			reg = <0x01c20058 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 			clock-output-names = "apb2";
 		};
 
@@ -331,7 +331,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc0",
 					     "mmc0_output",
 					     "mmc0_sample";
@@ -341,7 +341,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc1",
 					     "mmc1_output",
 					     "mmc1_sample";
@@ -351,7 +351,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc2",
 					     "mmc2_output",
 					     "mmc2_sample";
@@ -361,7 +361,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20094 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc3",
 					     "mmc3_output",
 					     "mmc3_sample";
@@ -371,7 +371,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c2009c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "ss";
 		};
 
@@ -379,7 +379,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a0 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi0";
 		};
 
@@ -387,7 +387,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a4 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi1";
 		};
 
@@ -395,7 +395,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a8 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi2";
 		};
 
@@ -403,7 +403,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200ac 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi3";
 		};
 
@@ -1042,8 +1042,8 @@
 			ar100: ar100_clk {
 				compatible = "allwinner,sun6i-a31-ar100-clk";
 				#clock-cells = <0>;
-				clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
-					 <&pll6 0>;
+				clocks = <&osc32k>, <&osc24M>, <&pll6>,
+					 <&pll6>;
 				clock-output-names = "ar100";
 			};
 
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 6f88fb0ddbc7..edc85eeaf365 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -60,7 +60,7 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&pll6 0>;
+			clocks = <&pll6>;
 			status = "disabled";
 		};
 	};
@@ -129,11 +129,20 @@
 		};
 
 		pll6: clk at 01c20028 {
-			#clock-cells = <1>;
+			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll6", "pll6x2";
+			clock-output-names = "pll6";
+		};
+
+                pll6x2: pll6x2_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll6>;
+			clock-output-names = "pll6-2x";
 		};
 
 		cpu: cpu_clk at 01c20050 {
@@ -163,7 +172,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 			clock-output-names = "ahb1";
 		};
 
@@ -190,7 +199,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-apb1-clk";
 			reg = <0x01c20058 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 			clock-output-names = "apb2";
 		};
 
@@ -213,7 +222,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc0",
 					     "mmc0_output",
 					     "mmc0_sample";
@@ -223,7 +232,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc1",
 					     "mmc1_output",
 					     "mmc1_sample";
@@ -233,7 +242,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "mmc2",
 					     "mmc2_output",
 					     "mmc2_sample";
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 92e6616979ea..5e589c1ddda9 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -79,7 +79,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-a23-mbus-clk";
 			reg = <0x01c2015c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+			clocks = <&osc24M>, <&pll6x2>, <&pll5>;
 			clock-output-names = "mbus";
 		};
 	};
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 001d8402ca18..f3eb618bcfa7 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -103,7 +103,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c2009c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>;
+			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "ss";
 		};
 
@@ -111,7 +111,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-a23-mbus-clk";
 			reg = <0x01c2015c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
+			clocks = <&osc24M>, <&pll6x2>, <&pll5>, <&pll11>;
 			clock-output-names = "mbus";
 		};
 	};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e43c9..19aadf47027d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -121,27 +121,27 @@
 		};
 
 		pll6: clk at 01c20028 {
-			#clock-cells = <1>;
+			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll6", "pll6x2";
+			clock-output-names = "pll6";
 		};
 
-		pll6d2: pll6d2_clk {
+		pll6x2: pll6x2_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
-			clock-div = <2>;
-			clock-mult = <1>;
-			clocks = <&pll6 0>;
-			clock-output-names = "pll6d2";
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll6>;
+			clock-output-names = "pll6-2x";
 		};
 
-		/* dummy clock until pll6 can be reused */
-		pll8: pll8_clk {
+		pll8: clk at 01c20044 {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c20044 0x4>;
+			clocks = <&osc24M>;
 			clock-output-names = "pll8";
 		};
 
@@ -165,7 +165,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 			clock-output-names = "ahb1";
 		};
 
@@ -173,7 +173,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-h3-ahb2-clk";
 			reg = <0x01c2005c 0x4>;
-			clocks = <&ahb1>, <&pll6d2>;
+			clocks = <&ahb1>, <&pll6>;
 			clock-output-names = "ahb2";
 		};
 
@@ -189,7 +189,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-apb1-clk";
 			reg = <0x01c20058 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 			clock-output-names = "apb2";
 		};
 
@@ -243,7 +243,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clocks = <&osc24M>, <&pll6>, <&pll8>;
 			clock-output-names = "mmc0",
 					     "mmc0_output",
 					     "mmc0_sample";
@@ -253,7 +253,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clocks = <&osc24M>, <&pll6>, <&pll8>;
 			clock-output-names = "mmc1",
 					     "mmc1_output",
 					     "mmc1_sample";
@@ -263,7 +263,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clocks = <&osc24M>, <&pll6>, <&pll8>;
 			clock-output-names = "mmc2",
 					     "mmc2_output",
 					     "mmc2_sample";
@@ -273,7 +273,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-a23-mbus-clk";
 			reg = <0x01c2015c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+			clocks = <&osc24M>, <&pll6x2>, <&pll5>;
 			clock-output-names = "mbus";
 		};
 	};
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index da15f2b12ab2..4de800e379d3 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -227,9 +227,9 @@ static void sun4i_get_pll5_factors(struct factors_request *req)
 }
 
 /**
- * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
- * PLL6x2 rate is calculated as follows
- * rate = parent_rate * (n + 1) * (k + 1)
+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
+ * PLL6 rate is calculated as follows
+ * rate = parent_rate * (n + 1) * (k + 1) / 2
  * parent_rate is always 24Mhz
  */
 
@@ -238,8 +238,8 @@ static void sun6i_a31_get_pll6_factors(struct factors_request *req)
 	u8 div;
 
 	/* Normalize value to a parent_rate multiple (24M) */
-	div = req->rate / req->parent_rate;
-	req->rate = req->parent_rate * div;
+	div = req->rate / (req->parent_rate / 2);
+	req->rate = (req->parent_rate / 2) * div;
 
 	req->k = div / 32;
 	if (req->k > 3)
@@ -248,6 +248,15 @@ static void sun6i_a31_get_pll6_factors(struct factors_request *req)
 	req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
 }
 
+static void sun6i_a31_pll6_recalc(struct factors_request *req)
+{
+	req->rate = req->parent_rate;
+
+	req->rate *= req->n + 1;
+	req->rate *= req->k + 1;
+	req->rate /= 2;
+}
+
 /**
  * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
  * AHB rate is calculated as follows
@@ -537,7 +546,7 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
 	.enable = 31,
 	.table = &sun6i_a31_pll6_config,
 	.getter = sun6i_a31_get_pll6_factors,
-	.name = "pll6x2",
+	.recalc = sun6i_a31_pll6_recalc,
 };
 
 static const struct factors_data sun5i_a13_ahb_data __initconst = {
@@ -788,15 +797,6 @@ static const struct divs_data pll6_divs_data __initconst = {
 	}
 };
 
-static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
-	.factors = &sun6i_a31_pll6_data,
-	.ndivs = 2,
-	.div = {
-		{ .fixed = 2 }, /* normal output */
-		{ .self = 1 }, /* base factor clock, 2x */
-	}
-};
-
 /**
  * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
  *
@@ -938,6 +938,7 @@ free_clkdata:
 static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
+	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
 	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
 	{.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
@@ -959,7 +960,6 @@ static const struct of_device_id clk_div_match[] __initconst = {
 static const struct of_device_id clk_divs_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 	{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
-	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
 	{}
 };
 
-- 
2.6.4

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 3:22 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Remove the fixed dividers from the PLL6 driver to be able to have a
> reusable driver that can be used across several SoCs that share the same
> controller, but don't have the same set of dividers for this clock, and to
> also be reused multiple times in the same SoC, since we're droping the
> clock name.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Changes from v2
>   - Rebased and converted over to the new factors refactoring. Fixed the
>     retrieved rate
>
>  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
>  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
>  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
>  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
>  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
>  6 files changed, 72 insertions(+), 63 deletions(-)

Please also update the #clock-cells section of
Documentation/devicetree/bindings/clock/sunxi.txt

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Jens Kuske]

Hi,

On 28/01/16 20:22, Maxime Ripard wrote:
> Remove the fixed dividers from the PLL6 driver to be able to have a
> reusable driver that can be used across several SoCs that share the same
> controller, but don't have the same set of dividers for this clock, and to
> also be reused multiple times in the same SoC, since we're droping the
> clock name.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Changes from v2
>   - Rebased and converted over to the new factors refactoring. Fixed the
>     retrieved rate
> 
>  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
>  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
>  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
>  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
>  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
>  6 files changed, 72 insertions(+), 63 deletions(-)
> 
[...]
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 1524130e43c9..19aadf47027d 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -121,27 +121,27 @@
>  		};
>  
>  		pll6: clk at 01c20028 {
> -			#clock-cells = <1>;
> +			#clock-cells = <0>;
>  			compatible = "allwinner,sun6i-a31-pll6-clk";
>  			reg = <0x01c20028 0x4>;
>  			clocks = <&osc24M>;
> -			clock-output-names = "pll6", "pll6x2";
> +			clock-output-names = "pll6";
>  		};
>  
> -		pll6d2: pll6d2_clk {
> +		pll6x2: pll6x2_clk {
>  			#clock-cells = <0>;
>  			compatible = "fixed-factor-clock";
> -			clock-div = <2>;
> -			clock-mult = <1>;
> -			clocks = <&pll6 0>;
> -			clock-output-names = "pll6d2";
> +			clock-div = <1>;
> +			clock-mult = <2>;
> +			clocks = <&pll6>;
> +			clock-output-names = "pll6-2x";
>  		};
>  
> -		/* dummy clock until pll6 can be reused */
> -		pll8: pll8_clk {
> +		pll8: clk at 01c20044 {
>  			#clock-cells = <0>;
> -			compatible = "fixed-clock";
> -			clock-frequency = <1>;
> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> +			reg = <0x01c20044 0x4>;
> +			clocks = <&osc24M>;
>  			clock-output-names = "pll8";
>  		};
>  
> @@ -165,7 +165,7 @@
>  			#clock-cells = <0>;
>  			compatible = "allwinner,sun6i-a31-ahb1-clk";
>  			reg = <0x01c20054 0x4>;
> -			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
>  			clock-output-names = "ahb1";
>  		};
>  
> @@ -173,7 +173,7 @@
>  			#clock-cells = <0>;
>  			compatible = "allwinner,sun8i-h3-ahb2-clk";
>  			reg = <0x01c2005c 0x4>;
> -			clocks = <&ahb1>, <&pll6d2>;
> +			clocks = <&ahb1>, <&pll6>;

According to the datasheet AHB2 really has PLL6 / 2 as parent, not PLL6
directly.

Jens

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 6:02 PM, Jens Kuske <jenskuske@gmail.com> wrote:
> Hi,
>
> On 28/01/16 20:22, Maxime Ripard wrote:
>> Remove the fixed dividers from the PLL6 driver to be able to have a
>> reusable driver that can be used across several SoCs that share the same
>> controller, but don't have the same set of dividers for this clock, and to
>> also be reused multiple times in the same SoC, since we're droping the
>> clock name.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> Changes from v2
>>   - Rebased and converted over to the new factors refactoring. Fixed the
>>     retrieved rate
>>
>>  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
>>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
>>  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
>>  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
>>  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
>>  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
>>  6 files changed, 72 insertions(+), 63 deletions(-)
>>
> [...]
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index 1524130e43c9..19aadf47027d 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -121,27 +121,27 @@
>>               };
>>
>>               pll6: clk at 01c20028 {
>> -                     #clock-cells = <1>;
>> +                     #clock-cells = <0>;
>>                       compatible = "allwinner,sun6i-a31-pll6-clk";
>>                       reg = <0x01c20028 0x4>;
>>                       clocks = <&osc24M>;
>> -                     clock-output-names = "pll6", "pll6x2";
>> +                     clock-output-names = "pll6";
>>               };
>>
>> -             pll6d2: pll6d2_clk {
>> +             pll6x2: pll6x2_clk {
>>                       #clock-cells = <0>;
>>                       compatible = "fixed-factor-clock";
>> -                     clock-div = <2>;
>> -                     clock-mult = <1>;
>> -                     clocks = <&pll6 0>;
>> -                     clock-output-names = "pll6d2";
>> +                     clock-div = <1>;
>> +                     clock-mult = <2>;
>> +                     clocks = <&pll6>;
>> +                     clock-output-names = "pll6-2x";
>>               };
>>
>> -             /* dummy clock until pll6 can be reused */
>> -             pll8: pll8_clk {
>> +             pll8: clk at 01c20044 {
>>                       #clock-cells = <0>;
>> -                     compatible = "fixed-clock";
>> -                     clock-frequency = <1>;
>> +                     compatible = "allwinner,sun6i-a31-pll6-clk";
>> +                     reg = <0x01c20044 0x4>;
>> +                     clocks = <&osc24M>;
>>                       clock-output-names = "pll8";
>>               };
>>
>> @@ -165,7 +165,7 @@
>>                       #clock-cells = <0>;
>>                       compatible = "allwinner,sun6i-a31-ahb1-clk";
>>                       reg = <0x01c20054 0x4>;
>> -                     clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> +                     clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
>>                       clock-output-names = "ahb1";
>>               };
>>
>> @@ -173,7 +173,7 @@
>>                       #clock-cells = <0>;
>>                       compatible = "allwinner,sun8i-h3-ahb2-clk";
>>                       reg = <0x01c2005c 0x4>;
>> -                     clocks = <&ahb1>, <&pll6d2>;
>> +                     clocks = <&ahb1>, <&pll6>;
>
> According to the datasheet AHB2 really has PLL6 / 2 as parent, not PLL6
> directly.

Thanks for the save. So we should keep pll6d2_clk.

ChenYu

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Maxime Ripard]

On Fri, Jan 29, 2016 at 06:14:48PM +0800, Chen-Yu Tsai wrote:
> >> @@ -173,7 +173,7 @@
> >>                       #clock-cells = <0>;
> >>                       compatible = "allwinner,sun8i-h3-ahb2-clk";
> >>                       reg = <0x01c2005c 0x4>;
> >> -                     clocks = <&ahb1>, <&pll6d2>;
> >> +                     clocks = <&ahb1>, <&pll6>;
> >
> > According to the datasheet AHB2 really has PLL6 / 2 as parent, not PLL6
> > directly.
> 
> Thanks for the save. So we should keep pll6d2_clk.

Indeed thanks for the review. Will fix for v4.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Jean-Francois Moine]

On Thu, 28 Jan 2016 20:22:38 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:

> Remove the fixed dividers from the PLL6 driver to be able to have a
> reusable driver that can be used across several SoCs that share the same
> controller, but don't have the same set of dividers for this clock, and to
> also be reused multiple times in the same SoC, since we're droping the
> clock name.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Changes from v2
>   - Rebased and converted over to the new factors refactoring. Fixed the
>     retrieved rate
> 
>  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
>  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
>  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
>  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
>  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
>  6 files changed, 72 insertions(+), 63 deletions(-)

Hi Maxime,

Do you know that the DT definitions cannot be changed when they are in
the mainline kernel?

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
'pll8x2' clock with 'pll8' as a divider?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 1:57 AM, Jean-Francois Moine <moinejf@free.fr> wrote:
> On Thu, 28 Jan 2016 20:22:38 +0100
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
>
>> Remove the fixed dividers from the PLL6 driver to be able to have a
>> reusable driver that can be used across several SoCs that share the same
>> controller, but don't have the same set of dividers for this clock, and to
>> also be reused multiple times in the same SoC, since we're droping the
>> clock name.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> Changes from v2
>>   - Rebased and converted over to the new factors refactoring. Fixed the
>>     retrieved rate
>>
>>  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
>>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
>>  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
>>  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
>>  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
>>  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
>>  6 files changed, 72 insertions(+), 63 deletions(-)
>
> Hi Maxime,
>
> Do you know that the DT definitions cannot be changed when they are in
> the mainline kernel?

This rule varies depending on who you talk to. :)

> Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
> 'pll8x2' clock with 'pll8' as a divider?

If it's used, it can be added later. No need to bloat the DT.


ChenYu

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Jean-Francois Moine]

On Sun, 31 Jan 2016 20:08:40 +0800
Chen-Yu Tsai <wens@csie.org> wrote:

> On Sun, Jan 31, 2016 at 1:57 AM, Jean-Francois Moine <moinejf@free.fr> wrote:
> > On Thu, 28 Jan 2016 20:22:38 +0100
> > Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> >
> >> Remove the fixed dividers from the PLL6 driver to be able to have a
> >> reusable driver that can be used across several SoCs that share the same
> >> controller, but don't have the same set of dividers for this clock, and to
> >> also be reused multiple times in the same SoC, since we're droping the
> >> clock name.
	[snip]
> > Hi Maxime,
> >
> > Do you know that the DT definitions cannot be changed when they are in
> > the mainline kernel?
> 
> This rule varies depending on who you talk to. :)
> 
> > Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
> > 'pll8x2' clock with 'pll8' as a divider?
> 
> If it's used, it can be added later. No need to bloat the DT.

In
	[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

  diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi

you may see:

> -		/* dummy clock until pll6 can be reused */
> -		pll8: pll8_clk {
> +		pll8: clk at 01c20044 {
>  			#clock-cells = <0>;
> -			compatible = "fixed-clock";
> -			clock-frequency = <1>;
> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> +			reg = <0x01c20044 0x4>;
> +			clocks = <&osc24M>;
>  			clock-output-names = "pll8";
>  		};

So, the pll periph1 is already there.

I was just saying that adding a pll8x2 would avoid changing the actual
pll6 and a lot of DT definitions.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Maxime Ripard]

Hi,

On Sat, Jan 30, 2016 at 06:57:14PM +0100, Jean-Francois Moine wrote:
> On Thu, 28 Jan 2016 20:22:38 +0100
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> 
> > Remove the fixed dividers from the PLL6 driver to be able to have a
> > reusable driver that can be used across several SoCs that share the same
> > controller, but don't have the same set of dividers for this clock, and to
> > also be reused multiple times in the same SoC, since we're droping the
> > clock name.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Changes from v2
> >   - Rebased and converted over to the new factors refactoring. Fixed the
> >     retrieved rate
> > 
> >  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
> >  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
> >  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
> >  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
> >  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
> >  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
> >  6 files changed, 72 insertions(+), 63 deletions(-)
> 
> Hi Maxime,
> 
> Do you know that the DT definitions cannot be changed when they are in
> the mainline kernel?

AFAIK, the only ARM platform that ever had such a policy was mvebu,
and they finally gave up on it. So, as far as I'm concerned, the DT
ABI simply doesn't exist.

> Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
> 'pll8x2' clock with 'pll8' as a divider?

No one seems to use it. We can always add it later in a separate
patch when someone will.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Jean-Francois Moine]

On Mon, 1 Feb 2016 21:17:54 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:

> > Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
> > 'pll8x2' clock with 'pll8' as a divider?
> 
> No one seems to use it. We can always add it later in a separate
> patch when someone will.

Well, then, I don't understand. The pll periph/peripheral/periph0,
aka PLL6 works well for many SoCs and there is no need to change
its DT definition.

In the patch header, you wrote:

> Remove the fixed dividers from the PLL6 driver to be able to have a
> reusable driver that can be used across several SoCs that share the same
> controller, but don't have the same set of dividers for this clock, and to
> also be reused multiple times in the same SoC, since we're droping the
> clock name.

then, for the H3, you do
(the comment should be "until pll8 can be reused"),

> -		/* dummy clock until pll6 can be reused */
> -		pll8: pll8_clk {
> +		pll8: clk at 01c20044 {
>  			#clock-cells = <0>;
> -			compatible = "fixed-clock";
> -			clock-frequency = <1>;
> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> +			reg = <0x01c20044 0x4>;
> +			clocks = <&osc24M>;
>  			clock-output-names = "pll8";
>  		};

that is, you add the PLL8, don't you?

And, further, you change the MMC clocks:

> @@ -243,7 +243,7 @@
>  			#clock-cells = <1>;
>  			compatible = "allwinner,sun4i-a10-mmc-clk";
>  			reg = <0x01c20088 0x4>;
> -			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clocks = <&osc24M>, <&pll6>, <&pll8>;
>  			clock-output-names = "mmc0",
>  					     "mmc0_output",
>  					     "mmc0_sample";

where the PLL8 is already used.

So, how can you say

> No one seems to use it. We can always add it later in a separate
> patch when someone will.

?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Maxime Ripard]

On Tue, Feb 02, 2016 at 07:52:39AM +0100, Jean-Francois Moine wrote:
> On Mon, 1 Feb 2016 21:17:54 +0100
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> 
> > > Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
> > > 'pll8x2' clock with 'pll8' as a divider?
> > 
> > No one seems to use it. We can always add it later in a separate
> > patch when someone will.
> 
> Well, then, I don't understand. The pll periph/peripheral/periph0,
> aka PLL6 works well for many SoCs and there is no need to change
> its DT definition.
> 
> In the patch header, you wrote:
> 
> > Remove the fixed dividers from the PLL6 driver to be able to have a
> > reusable driver that can be used across several SoCs that share the same
> > controller, but don't have the same set of dividers for this clock, and to
> > also be reused multiple times in the same SoC, since we're droping the
> > clock name.
> 
> then, for the H3, you do
> (the comment should be "until pll8 can be reused"),

No. The comment is right. Even though pll8 was just another instance
of pll6, the pll6 driver couldn't be reused because the clock name was
hardcoded in the driver, and you couldn't register two clocks with the
same name.

This was done because this driver has several outputs, the main PLL
output, plus all the various dividers it might have in the various
SoCs.

So, no. It was not working fine on "many" SoCs. And this is exactly
what this patch fixes.

> > -		/* dummy clock until pll6 can be reused */
> > -		pll8: pll8_clk {
> > +		pll8: clk at 01c20044 {
> >  			#clock-cells = <0>;
> > -			compatible = "fixed-clock";
> > -			clock-frequency = <1>;
> > +			compatible = "allwinner,sun6i-a31-pll6-clk";
> > +			reg = <0x01c20044 0x4>;
> > +			clocks = <&osc24M>;
> >  			clock-output-names = "pll8";
> >  		};
> 
> that is, you add the PLL8, don't you?

I guess it's just a matter of interpretation, but no, I'm just
removing the placeholder that was there.

> 
> And, further, you change the MMC clocks:
> 
> > @@ -243,7 +243,7 @@
> >  			#clock-cells = <1>;
> >  			compatible = "allwinner,sun4i-a10-mmc-clk";
> >  			reg = <0x01c20088 0x4>;
> > -			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> > +			clocks = <&osc24M>, <&pll6>, <&pll8>;
> >  			clock-output-names = "mmc0",
> >  					     "mmc0_output",
> >  					     "mmc0_sample";
> 
> where the PLL8 is already used.
> 
> So, how can you say
> 
> > No one seems to use it. We can always add it later in a separate
> > patch when someone will.

Because I was replying to a request from you asking about
pll8x2. The code you quote is about pll8...

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 1/2] clk: sunxi: factors: Add missing recalc pointer copy

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 3:22 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Commit 4a9b2abc213e ("clk: sunxi: factors: Support custom formulas") was
> introducing a custom recalc function. However, the pointer was never
> filled, which was making the whole thing unused.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

(facepalm)

Acked-by: Chen-Yu Tsai <wens@csie.org>

Can you squash it into the original?
Thanks


> ---
>  drivers/clk/sunxi/clk-factors.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
> index e480a6bcf1f6..6e97f46c0c37 100644
> --- a/drivers/clk/sunxi/clk-factors.c
> +++ b/drivers/clk/sunxi/clk-factors.c
> @@ -212,6 +212,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
>         factors->reg = reg;
>         factors->config = data->table;
>         factors->get_factors = data->getter;
> +       factors->recalc = data->recalc;
>         factors->lock = lock;
>
>         /* Add a gate if this factor clock can be gated */
> --
> 2.6.4
>

[PATCH v3 1/2] clk: sunxi: factors: Add missing recalc pointer copy

[Maxime Ripard]

On Fri, Jan 29, 2016 at 02:18:34PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 29, 2016 at 3:22 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Commit 4a9b2abc213e ("clk: sunxi: factors: Support custom formulas") was
> > introducing a custom recalc function. However, the pointer was never
> > filled, which was making the whole thing unused.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> (facepalm)
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> 
> Can you squash it into the original?

I just did, and pushed the updated branches.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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