* [RFC PATCH 1/4] PCI: Designware: Add support for ACPI based controllers
2016-02-04 11:37 [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers Gabriele Paoloni
@ 2016-02-04 11:37 ` Gabriele Paoloni
2016-02-04 11:37 ` [RFC PATCH 2/4] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI Gabriele Paoloni
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 11:37 UTC (permalink / raw)
To: linux-arm-kernel
From: gabriele paoloni <gabriele.paoloni@huawei.com>
This patch reworks the current Designware framework to
enable ACPI based controllers.
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/pci/host/pcie-designware.c | 39 +++++++++++++++++++++++++++++++++-----
drivers/pci/host/pcie-designware.h | 1 +
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 02a7452..4ced20d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -11,6 +11,7 @@
* published by the Free Software Foundation.
*/
+#include <linux/acpi.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
@@ -19,6 +20,7 @@
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
+#include <linux/pci-acpi.h>
#include <linux/pci_regs.h>
#include <linux/platform_device.h>
#include <linux/types.h>
@@ -46,7 +48,6 @@
#define PCIE_MSI_INTR0_ENABLE 0x828
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
-
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
@@ -69,7 +70,7 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
-static struct pci_ops dw_pcie_ops;
+struct pci_ops dw_pcie_ops;
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
{
@@ -657,8 +658,22 @@ static int dw_pcie_valid_config(struct pcie_port *pp,
static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
- struct pcie_port *pp = bus->sysdata;
int ret;
+ struct pcie_port *pp;
+ struct pci_bus *bridge_bus;
+
+ for (bridge_bus = bus; bridge_bus->parent;
+ bridge_bus = bridge_bus->parent)
+ ;
+
+ if (has_acpi_companion(bridge_bus->bridge)) {
+#ifdef CONFIG_ACPI_PCI_HOST_GENERIC
+ struct acpi_pci_root *root = bus->sysdata;
+
+ pp = root->sysdata;
+#endif /* CONFIG_ACPI_PCI_HOST_GENERIC */
+ } else
+ pp = bus->sysdata;
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
@@ -681,8 +696,22 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
- struct pcie_port *pp = bus->sysdata;
int ret;
+ struct pcie_port *pp;
+ struct pci_bus *bridge_bus;
+
+ for (bridge_bus = bus; bridge_bus->parent;
+ bridge_bus = bridge_bus->parent)
+ ;
+
+ if (has_acpi_companion(bridge_bus->bridge)) {
+#ifdef CONFIG_ACPI_PCI_HOST_GENERIC
+ struct acpi_pci_root *root = bus->sysdata;
+
+ pp = root->sysdata;
+#endif /* CONFIG_ACPI_PCI_HOST_GENERIC */
+ } else
+ pp = bus->sysdata;
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -700,7 +729,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return ret;
}
-static struct pci_ops dw_pcie_ops = {
+struct pci_ops dw_pcie_ops = {
.read = dw_pcie_rd_conf,
.write = dw_pcie_wr_conf,
};
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 2356d29..fd27fa4 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -80,4 +80,5 @@ int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+extern struct pci_ops dw_pcie_ops;
#endif /* _PCIE_DESIGNWARE_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC PATCH 2/4] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI
2016-02-04 11:37 [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers Gabriele Paoloni
2016-02-04 11:37 ` [RFC PATCH 1/4] PCI: Designware: Add support for ACPI based controllers Gabriele Paoloni
@ 2016-02-04 11:37 ` Gabriele Paoloni
2016-02-04 11:37 ` [RFC PATCH 3/4] PCI: hisi: Make the HiSilicon PCIe host controller ECAM compliant Gabriele Paoloni
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 11:37 UTC (permalink / raw)
To: linux-arm-kernel
From: gabriele paoloni <gabriele.paoloni@huawei.com>
re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
MAINTAINERS | 2 +
drivers/pci/host/Makefile | 2 +-
drivers/pci/host/pcie-hisi-common.c | 88 +++++++++++++++++++++++
drivers/pci/host/pcie-hisi.c | 135 ++++++------------------------------
drivers/pci/host/pcie-hisi.h | 44 ++++++++++++
5 files changed, 157 insertions(+), 114 deletions(-)
create mode 100644 drivers/pci/host/pcie-hisi-common.c
create mode 100644 drivers/pci/host/pcie-hisi.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c80d9ff..8d6ec25 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8247,7 +8247,9 @@ M: Gabriele Paoloni <gabriele.paoloni@huawei.com>
L: linux-pci at vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+F: drivers/pci/host/pcie-hisi.h
F: drivers/pci/host/pcie-hisi.c
+F: drivers/pci/host/pcie-hisi-common.c
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 9d4d3c6..6248320 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -19,4 +19,4 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
-obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
diff --git a/drivers/pci/host/pcie-hisi-common.c b/drivers/pci/host/pcie-hisi-common.c
new file mode 100644
index 0000000..ff93293
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-common.c
@@ -0,0 +1,88 @@
+/*
+ * PCIe host controller common functions for HiSilicon SoCs
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang <wangzhou1@hisilicon.com>
+ * Dacai Zhu <zhudacai@hisilicon.com>
+ * Gabriele Paoloni <gabriele.paoloni@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_pci.h>
+#include <linux/regmap.h>
+
+#include "pcie-designware.h"
+#include "pcie-hisi.h"
+
+/* HipXX PCIe host only supports 32-bit config access */
+static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
+ u32 *val)
+{
+ u32 reg;
+ u32 reg_val;
+ struct hisi_pcie *pcie = to_hisi_pcie(pp);
+ void *walker = ®_val;
+
+ walker += (where & 0x3);
+ reg = where & ~0x3;
+ reg_val = hisi_pcie_apb_readl(pcie, reg);
+
+ if (size == 1)
+ *val = *(u8 __force *) walker;
+ else if (size == 2)
+ *val = *(u16 __force *) walker;
+ else if (size == 4)
+ *val = reg_val;
+ else
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* HipXX PCIe host only supports 32-bit config access */
+static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
+ u32 val)
+{
+ u32 reg_val;
+ u32 reg;
+ struct hisi_pcie *pcie = to_hisi_pcie(pp);
+ void *walker = ®_val;
+
+ walker += (where & 0x3);
+ reg = where & ~0x3;
+ if (size == 4)
+ hisi_pcie_apb_writel(pcie, val, reg);
+ else if (size == 2) {
+ reg_val = hisi_pcie_apb_readl(pcie, reg);
+ *(u16 __force *) walker = val;
+ hisi_pcie_apb_writel(pcie, reg_val, reg);
+ } else if (size == 1) {
+ reg_val = hisi_pcie_apb_readl(pcie, reg);
+ *(u8 __force *) walker = val;
+ hisi_pcie_apb_writel(pcie, reg_val, reg);
+ } else
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int hisi_pcie_link_up(struct pcie_port *pp)
+{
+ struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
+
+ return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
+}
+
+struct pcie_host_ops hisi_pcie_host_ops = {
+ .rd_own_conf = hisi_pcie_cfg_read,
+ .wr_own_conf = hisi_pcie_cfg_write,
+ .link_up = hisi_pcie_link_up,
+};
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 3e98d4e..552ebfc 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -21,124 +21,13 @@
#include <linux/regmap.h>
#include "pcie-designware.h"
+#include "pcie-hisi.h"
#define PCIE_LTSSM_LINKUP_STATE 0x11
#define PCIE_LTSSM_STATE_MASK 0x3F
#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
-#define PCIE_SYS_STATE4 0x31c
#define PCIE_HIP06_CTRL_OFF 0x1000
-
-#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
-
-struct hisi_pcie;
-
-struct pcie_soc_ops {
- int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
-};
-
-struct hisi_pcie {
- struct regmap *subctrl;
- void __iomem *reg_base;
- u32 port_id;
- struct pcie_port pp;
- struct pcie_soc_ops *soc_ops;
-};
-
-static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
- u32 val, u32 reg)
-{
- writel(val, pcie->reg_base + reg);
-}
-
-static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
-{
- return readl(pcie->reg_base + reg);
-}
-
-/* HipXX PCIe host only supports 32-bit config access */
-static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
- u32 *val)
-{
- u32 reg;
- u32 reg_val;
- struct hisi_pcie *pcie = to_hisi_pcie(pp);
- void *walker = ®_val;
-
- walker += (where & 0x3);
- reg = where & ~0x3;
- reg_val = hisi_pcie_apb_readl(pcie, reg);
-
- if (size == 1)
- *val = *(u8 __force *) walker;
- else if (size == 2)
- *val = *(u16 __force *) walker;
- else if (size == 4)
- *val = reg_val;
- else
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-/* HipXX PCIe host only supports 32-bit config access */
-static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
- u32 val)
-{
- u32 reg_val;
- u32 reg;
- struct hisi_pcie *pcie = to_hisi_pcie(pp);
- void *walker = ®_val;
-
- walker += (where & 0x3);
- reg = where & ~0x3;
- if (size == 4)
- hisi_pcie_apb_writel(pcie, val, reg);
- else if (size == 2) {
- reg_val = hisi_pcie_apb_readl(pcie, reg);
- *(u16 __force *) walker = val;
- hisi_pcie_apb_writel(pcie, reg_val, reg);
- } else if (size == 1) {
- reg_val = hisi_pcie_apb_readl(pcie, reg);
- *(u8 __force *) walker = val;
- hisi_pcie_apb_writel(pcie, reg_val, reg);
- } else
- return PCIBIOS_BAD_REGISTER_NUMBER;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
-{
- u32 val;
-
- regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
- 0x100 * hisi_pcie->port_id, &val);
-
- return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
-}
-
-static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
-{
- u32 val;
-
- val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF +
- PCIE_SYS_STATE4);
-
- return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
-}
-
-static int hisi_pcie_link_up(struct pcie_port *pp)
-{
- struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
-
- return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
-}
-
-static struct pcie_host_ops hisi_pcie_host_ops = {
- .rd_own_conf = hisi_pcie_cfg_read,
- .wr_own_conf = hisi_pcie_cfg_write,
- .link_up = hisi_pcie_link_up,
-};
+#define PCIE_SYS_STATE4 0x31c
static int hisi_add_pcie_port(struct pcie_port *pp,
struct platform_device *pdev)
@@ -215,6 +104,26 @@ static int hisi_pcie_probe(struct platform_device *pdev)
return 0;
}
+static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
+{
+ u32 val;
+
+ regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
+ 0x100 * hisi_pcie->port_id, &val);
+
+ return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
+static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
+{
+ u32 val;
+
+ val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF +
+ PCIE_SYS_STATE4);
+
+ return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
static struct pcie_soc_ops hip05_ops = {
&hisi_pcie_link_up_hip05
};
diff --git a/drivers/pci/host/pcie-hisi.h b/drivers/pci/host/pcie-hisi.h
new file mode 100644
index 0000000..f64249d
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi.h
@@ -0,0 +1,44 @@
+/*
+ * PCIe host controller driver for HiSilicon SoCs
+ *
+ * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang <wangzhou1@hisilicon.com>
+ * Dacai Zhu <zhudacai@hisilicon.com>
+ * Gabriele Paoloni <gabriele.paoloni@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef PCIE_HISI_H_
+#define PCIE_HISI_H_
+
+struct hisi_pcie {
+ struct regmap *subctrl;
+ void __iomem *reg_base;
+ u32 port_id;
+ struct pcie_port pp;
+ struct pcie_soc_ops *soc_ops;
+};
+
+struct pcie_soc_ops {
+ int (*hisi_pcie_link_up)(struct hisi_pcie *pcie);
+};
+
+static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
+ u32 val, u32 reg)
+{
+ writel(val, pcie->reg_base + reg);
+}
+
+static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
+{
+ return readl(pcie->reg_base + reg);
+}
+
+#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
+
+extern struct pcie_host_ops hisi_pcie_host_ops;
+
+#endif /* PCIE_HISI_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC PATCH 3/4] PCI: hisi: Make the HiSilicon PCIe host controller ECAM compliant
2016-02-04 11:37 [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers Gabriele Paoloni
2016-02-04 11:37 ` [RFC PATCH 1/4] PCI: Designware: Add support for ACPI based controllers Gabriele Paoloni
2016-02-04 11:37 ` [RFC PATCH 2/4] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI Gabriele Paoloni
@ 2016-02-04 11:37 ` Gabriele Paoloni
2016-02-04 11:37 ` [RFC PATCH 4/4] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers Gabriele Paoloni
2016-02-04 13:11 ` [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe " Arnd Bergmann
4 siblings, 0 replies; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 11:37 UTC (permalink / raw)
To: linux-arm-kernel
From: gabriele paoloni <gabriele.paoloni@huawei.com>
This patch modifies the current Hip05/Hip06 PCIe host controller
driver to make it ECAM compliant. This is needed in preparation
for the ACPI based driver to allow both DT and ACPI drivers to
use the same BIOS (that configure the Designware iATUs).
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
.../devicetree/bindings/pci/hisilicon-pcie.txt | 4 ++--
drivers/pci/host/pcie-hisi-common.c | 15 +++++++++++++++
drivers/pci/host/pcie-hisi.c | 22 ++++++++++++++++++++++
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index b721bea..5c1bad0 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -23,8 +23,8 @@ Optional properties:
Hip05 Example (note that Hip06 is the same except compatible):
pcie at 0xb0080000 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
- reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
- reg-names = "rc_dbi", "config";
+ reg = <0 0xb0080000 0 0x10000>, <0x220 0x00100000 0 0x0f00000>;
+ reg-names = "rc_dbi", "ecam-cfg";
bus-range = <0 15>;
msi-parent = <&its_pcie>;
#address-cells = <3>;
diff --git a/drivers/pci/host/pcie-hisi-common.c b/drivers/pci/host/pcie-hisi-common.c
index ff93293..cbfb6c4 100644
--- a/drivers/pci/host/pcie-hisi-common.c
+++ b/drivers/pci/host/pcie-hisi-common.c
@@ -23,6 +23,19 @@
#include "pcie-hisi.h"
/* HipXX PCIe host only supports 32-bit config access */
+static int hisi_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 *value)
+{
+ return pci_generic_config_read(bus, devfn, where, size, value);
+}
+
+static int hisi_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+ unsigned int devfn, int where, int size, u32 value)
+{
+ return pci_generic_config_write(bus, devfn, where, size, value);
+}
+
+/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
u32 *val)
{
@@ -82,6 +95,8 @@ static int hisi_pcie_link_up(struct pcie_port *pp)
}
struct pcie_host_ops hisi_pcie_host_ops = {
+ .rd_other_conf = hisi_rd_other_conf,
+ .wr_other_conf = hisi_wr_other_conf,
.rd_own_conf = hisi_pcie_cfg_read,
.wr_own_conf = hisi_pcie_cfg_write,
.link_up = hisi_pcie_link_up,
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 552ebfc..1e45869 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -29,6 +29,18 @@
#define PCIE_HIP06_CTRL_OFF 0x1000
#define PCIE_SYS_STATE4 0x31c
+static void __iomem *hisi_pci_map_cfg_bus_cam(struct pci_bus *bus,
+ unsigned int devfn,
+ int where)
+{
+ void __iomem *addr;
+ struct pcie_port *pp = bus->sysdata;
+
+ addr = pp->va_cfg1_base + where;
+
+ return addr;
+}
+
static int hisi_add_pcie_port(struct pcie_port *pp,
struct platform_device *pdev)
{
@@ -48,6 +60,8 @@ static int hisi_add_pcie_port(struct pcie_port *pp,
pp->ops = &hisi_pcie_host_ops;
+ dw_pcie_ops.map_bus = hisi_pci_map_cfg_bus_cam;
+
ret = dw_pcie_host_init(pp);
if (ret) {
dev_err(&pdev->dev, "failed to initialize host\n");
@@ -93,6 +107,14 @@ static int hisi_pcie_probe(struct platform_device *pdev)
hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
+ reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam-cfg");
+ hisi_pcie->pp.va_cfg0_base = devm_ioremap_resource(&pdev->dev, reg);
+ if (IS_ERR(hisi_pcie->pp.va_cfg0_base)) {
+ dev_err(pp->dev, "cannot get ecam-cfg\n");
+ return PTR_ERR(hisi_pcie->pp.va_cfg0_base);
+ }
+ hisi_pcie->pp.va_cfg1_base = hisi_pcie->pp.va_cfg0_base;
+
ret = hisi_add_pcie_port(pp, pdev);
if (ret)
return ret;
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC PATCH 4/4] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers
2016-02-04 11:37 [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers Gabriele Paoloni
` (2 preceding siblings ...)
2016-02-04 11:37 ` [RFC PATCH 3/4] PCI: hisi: Make the HiSilicon PCIe host controller ECAM compliant Gabriele Paoloni
@ 2016-02-04 11:37 ` Gabriele Paoloni
2016-02-04 13:11 ` [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe " Arnd Bergmann
4 siblings, 0 replies; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 11:37 UTC (permalink / raw)
To: linux-arm-kernel
From: gabriele paoloni <gabriele.paoloni@huawei.com>
This patch adds specific quirks for PCI config space accessors,
it uses _HID to decide whether to hook pci_ops or not.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
MAINTAINERS | 1 +
drivers/pci/host/Kconfig | 9 +++
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-hisi-acpi.c | 147 ++++++++++++++++++++++++++++++++++++++
drivers/pci/host/pcie-hisi.c | 2 -
drivers/pci/host/pcie-hisi.h | 6 ++
6 files changed, 164 insertions(+), 2 deletions(-)
create mode 100644 drivers/pci/host/pcie-hisi-acpi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d6ec25..d35c300 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8250,6 +8250,7 @@ F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
F: drivers/pci/host/pcie-hisi.h
F: drivers/pci/host/pcie-hisi.c
F: drivers/pci/host/pcie-hisi-common.c
+F: drivers/pci/host/pcie-hisi-acpi.c
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 4d385d6..7a6b80d 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -174,4 +174,13 @@ config PCI_HISI
Say Y here if you want PCIe controller support on HiSilicon
Hip05 and Hip06 SoCs
+config PCI_HISI_ACPI
+ bool "ACPI PCI HiSilicon SoC HIP05 PCIe controller"
+ depends on ACPI
+ select ACPI_PCI_HOST_GENERIC
+ select PCIE_DW
+ help
+ Say Y here if you want ACPI PCIe controller support on
+ HiSilicon Hip05 and Hip06 SoCs
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6248320..ff010b6 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o
+obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o pcie-hisi-common.o
diff --git a/drivers/pci/host/pcie-hisi-acpi.c b/drivers/pci/host/pcie-hisi-acpi.c
new file mode 100644
index 0000000..1bca4f1
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi-acpi.c
@@ -0,0 +1,147 @@
+/*
+ * PCIe host controller driver for HiSilicon HipXX SoCs
+ *
+ * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Dongdong Liu <liudongdong3@huawei.com>
+ * Gabriele Paoloni <gabriele.paoloni@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/interrupt.h>
+#include <linux/acpi.h>
+#include <linux/ecam.h>
+#include <linux/pci.h>
+#include <linux/pci-acpi.h>
+#include "pcie-designware.h"
+#include "pcie-hisi.h"
+
+#define GET_PCIE_LINK_STATUS 0x0
+
+/* uuid 6d30f553-836c-408e-b6ad-45bccc957949 */
+const u8 hisi_pcie_acpi_dsm_uuid[] = {
+ 0x53, 0xf5, 0x30, 0x6d, 0x6c, 0x83, 0x8e, 0x40,
+ 0xb6, 0xad, 0x45, 0xbc, 0xcc, 0x95, 0x79, 0x49
+};
+
+static const struct acpi_device_id hisi_pcie_ids[] = {
+ {"HISI0080", 0},
+ {"", 0},
+};
+
+static int hisi_pcie_get_addr(struct acpi_pci_root *root, const char *name,
+ void __iomem **addr)
+{
+ struct acpi_device *device;
+ u64 base;
+ u64 size;
+ u32 buf[4];
+ int ret;
+
+ device = root->device;
+ ret = fwnode_property_read_u32_array(&device->fwnode, name,
+ buf, ARRAY_SIZE(buf));
+ if (ret) {
+ dev_err(&device->dev, "can't get %s\n", name);
+ return ret;
+ }
+
+ base = ((u64)buf[0] << 32) | buf[1];
+ size = ((u64)buf[2] << 32) | buf[3];
+ *addr = devm_ioremap(&device->dev, base, size);
+ if (!(*addr)) {
+ dev_err(&device->dev, "error with ioremap\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+
+static int hisi_pcie_link_up_acpi(struct hisi_pcie *hisi_pcie)
+{
+ u32 val;
+
+ struct acpi_pci_root *root;
+ struct acpi_device *device;
+ union acpi_object *obj;
+
+ root = hisi_pcie->root;
+ device = root->device;
+ obj = acpi_evaluate_dsm(device->handle,
+ hisi_pcie_acpi_dsm_uuid, 0,
+ GET_PCIE_LINK_STATUS, NULL);
+
+ if (!obj || obj->type != ACPI_TYPE_INTEGER) {
+ dev_err(&device->dev, "can't get link status from _DSM\n");
+ return 0;
+ }
+ val = obj->integer.value;
+
+ return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+
+}
+
+static struct pcie_soc_ops acpi_ops = {
+ &hisi_pcie_link_up_acpi
+};
+
+/*
+ * Retrieve rc_dbi base and size from _DSD
+ * Name (_DSD, Package () {
+ * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ * Package () {
+ * Package () {"rc-dbi", Package () { 0x0, 0xb0080000, 0x0, 0x10000 }},
+ * }
+ * })
+ */
+static int hisi_pcie_init(struct acpi_pci_root *root)
+{
+ struct hisi_pcie *pcie;
+ int ret;
+ struct acpi_device *device;
+
+ device = root->device;
+ pcie = devm_kzalloc(&device->dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ ret = hisi_pcie_get_addr(root, "rc-dbi", &pcie->reg_base);
+ if (ret) {
+ dev_err(&device->dev, "can't get rc-dbi\n");
+ return ret;
+ }
+
+ pcie->pp.dbi_base = pcie->reg_base;
+ pcie->pp.root_bus_nr = root->secondary.start;
+ pcie->pp.ops = &hisi_pcie_host_ops;
+ pcie->root = root;
+ pcie->soc_ops = &acpi_ops;
+ root->sysdata = &pcie->pp;
+ return 0;
+}
+
+static int hisi_pcie_match(struct pci_mcfg_fixup *fixup,
+ struct acpi_pci_root *root)
+{
+ int ret;
+ struct acpi_device *device;
+
+ device = root->device;
+ ret = acpi_match_device_ids(device, hisi_pcie_ids);
+ if (ret)
+ return 0;
+
+ ret = hisi_pcie_init(root);
+ if (ret)
+ dev_warn(&device->dev, "hisi pcie init fail\n");
+
+ dw_pcie_ops.map_bus = pci_mcfg_dev_base;
+
+ return 1;
+}
+
+DECLARE_ACPI_MCFG_FIXUP(NULL, hisi_pcie_match, &dw_pcie_ops,
+ PCI_MCFG_DOMAIN_ANY, PCI_MCFG_BUS_ANY);
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index 1e45869..d7867cf 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -23,8 +23,6 @@
#include "pcie-designware.h"
#include "pcie-hisi.h"
-#define PCIE_LTSSM_LINKUP_STATE 0x11
-#define PCIE_LTSSM_STATE_MASK 0x3F
#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
#define PCIE_HIP06_CTRL_OFF 0x1000
#define PCIE_SYS_STATE4 0x31c
diff --git a/drivers/pci/host/pcie-hisi.h b/drivers/pci/host/pcie-hisi.h
index f64249d..396deb2 100644
--- a/drivers/pci/host/pcie-hisi.h
+++ b/drivers/pci/host/pcie-hisi.h
@@ -15,6 +15,9 @@
#define PCIE_HISI_H_
struct hisi_pcie {
+#ifdef CONFIG_PCI_HISI_ACPI
+ struct acpi_pci_root *root;
+#endif /* CONFIG_ACPI_HOST_GENERIC */
struct regmap *subctrl;
void __iomem *reg_base;
u32 port_id;
@@ -41,4 +44,7 @@ static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
extern struct pcie_host_ops hisi_pcie_host_ops;
+#define PCIE_LTSSM_LINKUP_STATE 0x11
+#define PCIE_LTSSM_STATE_MASK 0x3F
+
#endif /* PCIE_HISI_H_ */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 11:37 [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers Gabriele Paoloni
` (3 preceding siblings ...)
2016-02-04 11:37 ` [RFC PATCH 4/4] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers Gabriele Paoloni
@ 2016-02-04 13:11 ` Arnd Bergmann
2016-02-04 15:11 ` Gabriele Paoloni
4 siblings, 1 reply; 15+ messages in thread
From: Arnd Bergmann @ 2016-02-04 13:11 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 04 February 2016 19:37:36 Gabriele Paoloni wrote:
> From: gabriele paoloni <gabriele.paoloni@huawei.com>
>
> This patchset adds ACPI support for the HiSilicon Hip05/Hip06 SoC PCIe controllers
> The four patches respectively:
> - rework PCie Designware to be used for ACPI PCI Host controllers
> - re-architect the current HiSilicon driver to make it scalable to the
> new ACPI quirks
> - rework the current HiSilicon driver to make it ECAM compliant
> - adds the HiSilicon ACPI specific quirks.
>
> This patchset is based on
> https://github.com/semihalf-nowicki-tomasz/linux.git
> branch pci-acpi-v3 + Hip06 support applied on top:
> https://patchwork.ozlabs.org/patch/549198/
>
ACPI has its own PCI support, and should not need drivers for host
bridges. I don't think we can really mix the two things, as ACPI
needs to have access to things like PCI config space way before
we are probing normal device drivers.
Please put this in drivers/acpi/pci*.c.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 13:11 ` [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe " Arnd Bergmann
@ 2016-02-04 15:11 ` Gabriele Paoloni
2016-02-04 16:07 ` Arnd Bergmann
0 siblings, 1 reply; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 15:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd
Thanks for looking at this
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: 04 February 2016 13:12
> To: Gabriele Paoloni
> Cc: Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong (C); Linuxarm;
> qiujiang; bhelgaas at google.com; Lorenzo.Pieralisi at arm.com;
> tn at semihalf.com; zhangjukuo; xuwei (O); Liguozhu (Kenneth); linux-
> pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> acpi at vger.kernel.org; linux-kernel at vger.kernel.org; jcm at redhat.com
> Subject: Re: [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host
> Controllers
>
> On Thursday 04 February 2016 19:37:36 Gabriele Paoloni wrote:
> > From: gabriele paoloni <gabriele.paoloni@huawei.com>
> >
> > This patchset adds ACPI support for the HiSilicon Hip05/Hip06 SoC
> PCIe controllers
> > The four patches respectively:
> > - rework PCie Designware to be used for ACPI PCI Host
> controllers
> > - re-architect the current HiSilicon driver to make it
> scalable to the
> > new ACPI quirks
> > - rework the current HiSilicon driver to make it ECAM
> compliant
> > - adds the HiSilicon ACPI specific quirks.
> >
> > This patchset is based on
> > https://github.com/semihalf-nowicki-tomasz/linux.git
> > branch pci-acpi-v3 + Hip06 support applied on top:
> > https://patchwork.ozlabs.org/patch/549198/
> >
>
> ACPI has its own PCI support, and should not need drivers for host
> bridges. I don't think we can really mix the two things, as ACPI
> needs to have access to things like PCI config space way before
> we are probing normal device drivers.
>
> Please put this in drivers/acpi/pci*.c.
I can put pcie-hisi-acpi.c under drivers/acpi/
However if you look at the driver it is made up of three parts:
pcie-hisi.c --> the DT based driver
pcie-hisi-acpi.c --> the ACPI based hook and ACPI specific init callback
pcie-hisi-common.c --> common functions shared between DT and ACPI versions
of the driver
Now I think that moving pcie-hisi-acpi.c under drivers/acpi/
would make it hard to read as you need to jump across directories
and it seems a bit unnatural...
However it is not a big issue to me...
Cheers
Gab
>
> Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 15:11 ` Gabriele Paoloni
@ 2016-02-04 16:07 ` Arnd Bergmann
2016-02-04 16:44 ` Gabriele Paoloni
0 siblings, 1 reply; 15+ messages in thread
From: Arnd Bergmann @ 2016-02-04 16:07 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 04 February 2016 15:11:18 Gabriele Paoloni wrote:
> >
> > ACPI has its own PCI support, and should not need drivers for host
> > bridges. I don't think we can really mix the two things, as ACPI
> > needs to have access to things like PCI config space way before
> > we are probing normal device drivers.
> >
> > Please put this in drivers/acpi/pci*.c.
>
> I can put pcie-hisi-acpi.c under drivers/acpi/
>
> However if you look at the driver it is made up of three parts:
> pcie-hisi.c --> the DT based driver
> pcie-hisi-acpi.c --> the ACPI based hook and ACPI specific init callback
> pcie-hisi-common.c --> common functions shared between DT and ACPI versions
> of the driver
>
> Now I think that moving pcie-hisi-acpi.c under drivers/acpi/
> would make it hard to read as you need to jump across directories
> and it seems a bit unnatural...
>
> However it is not a big issue to me...
That's not really what I meant though: the pcie-hisi driver uses the
pcie-designware.c library, most of which makes no sense in an environment
where you have ACPI, e.g. link training, custom MSI support, initial
register setup, platform driver hooks, etc.
You should add a very minimal set of hacks for the parts in this driver
that diverge from a standard SBSA compliant PCIe host that ACPI expects.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 16:07 ` Arnd Bergmann
@ 2016-02-04 16:44 ` Gabriele Paoloni
2016-02-04 17:01 ` Arnd Bergmann
0 siblings, 1 reply; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 16:44 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: 04 February 2016 16:07
> To: Gabriele Paoloni
> Cc: Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong (C); Linuxarm;
> qiujiang; bhelgaas at google.com; Lorenzo.Pieralisi at arm.com;
> tn at semihalf.com; zhangjukuo; xuwei (O); Liguozhu (Kenneth); linux-
> pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> acpi at vger.kernel.org; linux-kernel at vger.kernel.org; jcm at redhat.com
> Subject: Re: [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host
> Controllers
>
> On Thursday 04 February 2016 15:11:18 Gabriele Paoloni wrote:
> > >
> > > ACPI has its own PCI support, and should not need drivers for host
> > > bridges. I don't think we can really mix the two things, as ACPI
> > > needs to have access to things like PCI config space way before
> > > we are probing normal device drivers.
> > >
> > > Please put this in drivers/acpi/pci*.c.
> >
> > I can put pcie-hisi-acpi.c under drivers/acpi/
> >
> > However if you look at the driver it is made up of three parts:
> > pcie-hisi.c --> the DT based driver
> > pcie-hisi-acpi.c --> the ACPI based hook and ACPI specific init
> callback
> > pcie-hisi-common.c --> common functions shared between DT and ACPI
> versions
> > of the driver
> >
> > Now I think that moving pcie-hisi-acpi.c under drivers/acpi/
> > would make it hard to read as you need to jump across directories
> > and it seems a bit unnatural...
> >
> > However it is not a big issue to me...
>
> That's not really what I meant though: the pcie-hisi driver uses the
> pcie-designware.c library, most of which makes no sense in an
> environment
> where you have ACPI, e.g. link training, custom MSI support, initial
> register setup, platform driver hooks, etc.
>
> You should add a very minimal set of hacks for the parts in this driver
> that diverge from a standard SBSA compliant PCIe host that ACPI expects.
Effectively the ACPI version of the HiSilicon driver does not rely on
Designware as much as the DT version (that calls dw_pcie_host_init());
however in order to do what you suggest I'd need to copy and paste and
modify dw_pcie_rd_conf and dw_pcie_wr_conf.
Also I'd need to declare duplicate version of the functions in
pcie-hisi-common.c (if I do not want to split the object across
different paths "drivers/pci/host" and "drivers/acpi/")
Now I can do it but I thought it was more correct to pass &dw_pcie_ops
as input pointer in DECLARE_ACPI_MCFG_FIXUP(); this is also because maybe in
future other Designware based controllers may need to support ACPI and it
would be easier for them to reuse their DT based driver functions
Honestly I am a bit confused...
Thanks
Gab
>
> Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 16:44 ` Gabriele Paoloni
@ 2016-02-04 17:01 ` Arnd Bergmann
2016-02-04 17:06 ` Gabriele Paoloni
2016-02-08 13:17 ` Gabriele Paoloni
0 siblings, 2 replies; 15+ messages in thread
From: Arnd Bergmann @ 2016-02-04 17:01 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 04 February 2016 16:44:12 Gabriele Paoloni wrote:
> Effectively the ACPI version of the HiSilicon driver does not rely on
> Designware as much as the DT version (that calls dw_pcie_host_init());
> however in order to do what you suggest I'd need to copy and paste and
> modify dw_pcie_rd_conf and dw_pcie_wr_conf.
> Also I'd need to declare duplicate version of the functions in
> pcie-hisi-common.c (if I do not want to split the object across
> different paths "drivers/pci/host" and "drivers/acpi/")
>
> Now I can do it but I thought it was more correct to pass &dw_pcie_ops
> as input pointer in DECLARE_ACPI_MCFG_FIXUP(); this is also because maybe in
> future other Designware based controllers may need to support ACPI and it
> would be easier for them to reuse their DT based driver functions
>
> Honestly I am a bit confused...
>
I don't think you can use the dw_pcie_ops as-is anyway, as they in
turn rely on the device driver structure, and you also don't need
those as they seem to be written for the generic case of a 32-bit
architecture that does not have enough space to map the entire
config space into MMIO. Just set up all those mapping registers from
the firmware and pass the config space base address as you'd normally
do on ACPI.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 17:01 ` Arnd Bergmann
@ 2016-02-04 17:06 ` Gabriele Paoloni
2016-02-08 13:17 ` Gabriele Paoloni
1 sibling, 0 replies; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-04 17:06 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: 04 February 2016 17:02
> To: Gabriele Paoloni
> Cc: Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong (C); Linuxarm;
> qiujiang; bhelgaas at google.com; Lorenzo.Pieralisi at arm.com;
> tn at semihalf.com; zhangjukuo; xuwei (O); Liguozhu (Kenneth); linux-
> pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> acpi at vger.kernel.org; linux-kernel at vger.kernel.org; jcm at redhat.com
> Subject: Re: [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host
> Controllers
>
> On Thursday 04 February 2016 16:44:12 Gabriele Paoloni wrote:
> > Effectively the ACPI version of the HiSilicon driver does not rely on
> > Designware as much as the DT version (that calls
> dw_pcie_host_init());
> > however in order to do what you suggest I'd need to copy and paste
> and
> > modify dw_pcie_rd_conf and dw_pcie_wr_conf.
> > Also I'd need to declare duplicate version of the functions in
> > pcie-hisi-common.c (if I do not want to split the object across
> > different paths "drivers/pci/host" and "drivers/acpi/")
> >
> > Now I can do it but I thought it was more correct to pass
> &dw_pcie_ops
> > as input pointer in DECLARE_ACPI_MCFG_FIXUP(); this is also because
> maybe in
> > future other Designware based controllers may need to support ACPI
> and it
> > would be easier for them to reuse their DT based driver functions
> >
> > Honestly I am a bit confused...
> >
>
> I don't think you can use the dw_pcie_ops as-is anyway, as they in
> turn rely on the device driver structure, and you also don't need
> those as they seem to be written for the generic case of a 32-bit
> architecture that does not have enough space to map the entire
> config space into MMIO. Just set up all those mapping registers from
> the firmware and pass the config space base address as you'd normally
> do on ACPI.
Ok thanks, I'll wait a bit to see if there is any comment on this
from other people, if not I'll rework the ACPI driver as you suggest
and remove any dependency on Designware.
Cheers
Gab
>
> Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-04 17:01 ` Arnd Bergmann
2016-02-04 17:06 ` Gabriele Paoloni
@ 2016-02-08 13:17 ` Gabriele Paoloni
2016-02-08 13:55 ` Arnd Bergmann
1 sibling, 1 reply; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-08 13:17 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: 04 February 2016 17:02
> To: Gabriele Paoloni
> Cc: Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong (C); Linuxarm;
> qiujiang; bhelgaas at google.com; Lorenzo.Pieralisi at arm.com;
> tn at semihalf.com; zhangjukuo; xuwei (O); Liguozhu (Kenneth); linux-
> pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> acpi at vger.kernel.org; linux-kernel at vger.kernel.org; jcm at redhat.com
> Subject: Re: [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host
> Controllers
>
> On Thursday 04 February 2016 16:44:12 Gabriele Paoloni wrote:
> > Effectively the ACPI version of the HiSilicon driver does not rely on
> > Designware as much as the DT version (that calls
> dw_pcie_host_init());
> > however in order to do what you suggest I'd need to copy and paste
> and
> > modify dw_pcie_rd_conf and dw_pcie_wr_conf.
> > Also I'd need to declare duplicate version of the functions in
> > pcie-hisi-common.c (if I do not want to split the object across
> > different paths "drivers/pci/host" and "drivers/acpi/")
> >
> > Now I can do it but I thought it was more correct to pass
> &dw_pcie_ops
> > as input pointer in DECLARE_ACPI_MCFG_FIXUP(); this is also because
> maybe in
> > future other Designware based controllers may need to support ACPI
> and it
> > would be easier for them to reuse their DT based driver functions
> >
> > Honestly I am a bit confused...
> >
>
> I don't think you can use the dw_pcie_ops as-is anyway, as they in
> turn rely on the device driver structure, and you also don't need
> those as they seem to be written for the generic case of a 32-bit
> architecture that does not have enough space to map the entire
> config space into MMIO. Just set up all those mapping registers from
> the firmware and pass the config space base address as you'd normally
> do on ACPI.
Hi Arnd
I have now sent out patchset v2.
Now I have removed the dependency from designware but I still think
the best location for the code is in "drivers/pci/host/":
the ACPI quirks share the config read/write functions with the DT
driver, moreover for other hosts in future I think it makes sense
to stay in "drivers/pci/host/" as they could even share more init
code with their respective DT versions...
Cheers
Gab
>
> Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-08 13:17 ` Gabriele Paoloni
@ 2016-02-08 13:55 ` Arnd Bergmann
2016-02-08 14:11 ` Sinan Kaya
0 siblings, 1 reply; 15+ messages in thread
From: Arnd Bergmann @ 2016-02-08 13:55 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 08 February 2016 13:17:58 Gabriele Paoloni wrote:
>
> Now I have removed the dependency from designware but I still think
> the best location for the code is in "drivers/pci/host/":
> the ACPI quirks share the config read/write functions with the DT
> driver, moreover for other hosts in future I think it makes sense
> to stay in "drivers/pci/host/" as they could even share more init
> code with their respective DT versions...
I haven't really followed what is going on with ACPI. Do you expect
to see future machines come out that are not just implementing SBSA
but that still need to run ACPI? I thought this was just a hack
for some early machines that only run with ACPI but are not actually
compliant.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-08 13:55 ` Arnd Bergmann
@ 2016-02-08 14:11 ` Sinan Kaya
2016-02-08 16:20 ` Gabriele Paoloni
0 siblings, 1 reply; 15+ messages in thread
From: Sinan Kaya @ 2016-02-08 14:11 UTC (permalink / raw)
To: linux-arm-kernel
On 2/8/2016 8:55 AM, Arnd Bergmann wrote:
> I haven't really followed what is going on with ACPI. Do you expect
> to see future machines come out that are not just implementing SBSA
> but that still need to run ACPI? I thought this was just a hack
> for some early machines that only run with ACPI but are not actually
> compliant.
>
> Arnd
I agree. We shouldn't be playing with half-baked ACPI solutions. We have seen
two variants already that claim to be ACPI compliant yet they do not tie into
anything inside ACPICA.
The correct route is to use Tomasz's ACPI PCI root bridge driver and use the ACPI
framework.
If a platform has quirks, Tomasz's patches allow vendors add quirks too.
The combination of PCI host bridge driver + ACPI hack is not right.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host Controllers
2016-02-08 14:11 ` Sinan Kaya
@ 2016-02-08 16:20 ` Gabriele Paoloni
0 siblings, 0 replies; 15+ messages in thread
From: Gabriele Paoloni @ 2016-02-08 16:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Sinan
> -----Original Message-----
> From: Sinan Kaya [mailto:okaya at codeaurora.org]
> Sent: 08 February 2016 14:12
> To: Arnd Bergmann; linux-arm-kernel at lists.infradead.org
> Cc: Gabriele Paoloni; Lorenzo.Pieralisi at arm.com; jcm at redhat.com;
> tn at semihalf.com; linux-pci at vger.kernel.org; Linuxarm; xuwei (O); linux-
> kernel at vger.kernel.org; linux-acpi at vger.kernel.org; Wangzhou (B);
> liudongdong (C); Guohanjun (Hanjun Guo); bhelgaas at google.com;
> zhangjukuo; Liguozhu (Kenneth); qiujiang
> Subject: Re: [RFC PATCH 0/4] Add ACPI support for HiSilicon PCIe Host
> Controllers
>
> On 2/8/2016 8:55 AM, Arnd Bergmann wrote:
> > I haven't really followed what is going on with ACPI. Do you expect
> > to see future machines come out that are not just implementing SBSA
> > but that still need to run ACPI? I thought this was just a hack
> > for some early machines that only run with ACPI but are not actually
> > compliant.
Well from our side (HiSilicon) we're trying to move away from non fully
ECAM platforms, so from us in the long term I don't expect too many quirks,
but I don't know about the other vendors.
Obviously the reason why Tomasz implemented the quirks is to fit non
fully ECAM HW and to allow custom HW init; this is why I thought better
to have the ACPI version in the same dir as the DT (maybe we can create
an ACPI sub-dir in drivers/pci/host ?)
> >
> > Arnd
>
> I agree. We shouldn't be playing with half-baked ACPI solutions. We
> have seen
> two variants already that claim to be ACPI compliant yet they do not
> tie into
> anything inside ACPICA.
>
> The correct route is to use Tomasz's ACPI PCI root bridge driver and
> use the ACPI
> framework.
>
> If a platform has quirks, Tomasz's patches allow vendors add quirks
> too.
>
> The combination of PCI host bridge driver + ACPI hack is not right.
If you look at my patchset you can see that I didn't do any hack,
I just used the framework provided by Tomasz patchset.
The discussion here is more about the code location for the quirks.
Since the configuration read/write and the HW init sequences can be
similar between the ACPI variant and DT variant I thought it make
sense to have them in "drivers/pci/host"
Thanks
Gab
>
> --
> Sinan Kaya
> Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center,
> Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
> Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 15+ messages in thread