* [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
@ 2016-02-12 7:11 Dirk Behme
2016-02-12 14:16 ` Russell King - ARM Linux
0 siblings, 1 reply; 6+ messages in thread
From: Dirk Behme @ 2016-02-12 7:11 UTC (permalink / raw)
To: linux-arm-kernel
All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.
For the i.MX6 specific L2 cache handling we missed this check.
Add it.
Signed-off-by: Marcel Grosshans <MarcelViktor.Grosshans@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
---
arch/arm/mach-imx/system.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 51c3501..a600bd7 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -106,6 +106,9 @@ void __init imx_init_l2cache(void)
goto out;
}
+ if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
+ goto skip_if_enabled;
+
/* Configure the L2 PREFETCH and POWER registers */
val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
val |= 0x70800000;
@@ -122,6 +125,7 @@ void __init imx_init_l2cache(void)
val &= ~(1 << 30 | 1 << 23);
writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
+skip_if_enabled:
iounmap(l2x0_base);
of_node_put(np);
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
2016-02-12 7:11 [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled Dirk Behme
@ 2016-02-12 14:16 ` Russell King - ARM Linux
2016-02-12 15:51 ` Dirk Behme
0 siblings, 1 reply; 6+ messages in thread
From: Russell King - ARM Linux @ 2016-02-12 14:16 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
> All the generic L2 cache handling code is encapsulated by a
> check if the L2 cache is enabled. If it's enabled already, the code
> is skipped.
>
> For the i.MX6 specific L2 cache handling we missed this check.
> Add it.
What's the reasoning behind this? The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.
--
RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
2016-02-12 14:16 ` Russell King - ARM Linux
@ 2016-02-12 15:51 ` Dirk Behme
2016-02-14 8:18 ` Shawn Guo
0 siblings, 1 reply; 6+ messages in thread
From: Dirk Behme @ 2016-02-12 15:51 UTC (permalink / raw)
To: linux-arm-kernel
On 12.02.2016 15:16, Russell King - ARM Linux wrote:
> On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
>> All the generic L2 cache handling code is encapsulated by a
>> check if the L2 cache is enabled. If it's enabled already, the code
>> is skipped.
>>
>> For the i.MX6 specific L2 cache handling we missed this check.
>> Add it.
>
> What's the reasoning behind this? The prefetch register is writable
> while the L2 cache is enabled, unlike the auxiliary control register.
From an internal log I have the following info:
The write to the L2-Cache controller from non-secure world causes an
imprecise
external abort. If Linux runs from normal world the cache controller
is already
enabled and thus no configuration is needed by Linux.
Best regards
Dirk
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
2016-02-12 15:51 ` Dirk Behme
@ 2016-02-14 8:18 ` Shawn Guo
2016-02-14 8:30 ` Dirk Behme
0 siblings, 1 reply; 6+ messages in thread
From: Shawn Guo @ 2016-02-14 8:18 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:
> On 12.02.2016 15:16, Russell King - ARM Linux wrote:
> >On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
> >>All the generic L2 cache handling code is encapsulated by a
> >>check if the L2 cache is enabled. If it's enabled already, the code
> >>is skipped.
> >>
> >>For the i.MX6 specific L2 cache handling we missed this check.
> >>Add it.
> >
> >What's the reasoning behind this? The prefetch register is writable
> >while the L2 cache is enabled, unlike the auxiliary control register.
>
> From an internal log I have the following info:
>
> The write to the L2-Cache controller from non-secure world causes an
> imprecise
> external abort. If Linux runs from normal world the cache controller
> is already
> enabled and thus no configuration is needed by Linux.
Dirk,
Do you have a real use case of this, i.e. running Linux on i.MX6 in
non-secure world?
Shawn
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
2016-02-14 8:18 ` Shawn Guo
@ 2016-02-14 8:30 ` Dirk Behme
2016-02-18 14:57 ` Shawn Guo
0 siblings, 1 reply; 6+ messages in thread
From: Dirk Behme @ 2016-02-14 8:30 UTC (permalink / raw)
To: linux-arm-kernel
On 14.02.2016 09:18, Shawn Guo wrote:
> On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:
>> On 12.02.2016 15:16, Russell King - ARM Linux wrote:
>>> On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
>>>> All the generic L2 cache handling code is encapsulated by a
>>>> check if the L2 cache is enabled. If it's enabled already, the code
>>>> is skipped.
>>>>
>>>> For the i.MX6 specific L2 cache handling we missed this check.
>>>> Add it.
>>>
>>> What's the reasoning behind this? The prefetch register is writable
>>> while the L2 cache is enabled, unlike the auxiliary control register.
>>
>> From an internal log I have the following info:
>>
>> The write to the L2-Cache controller from non-secure world causes an
>> imprecise
>> external abort. If Linux runs from normal world the cache controller
>> is already
>> enabled and thus no configuration is needed by Linux.
>
> Dirk,
>
> Do you have a real use case of this, i.e. running Linux on i.MX6 in
> non-secure world?
Yes, in a scenario where one of the cores runs a RTOS.
Best regards
Dirk
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
2016-02-14 8:30 ` Dirk Behme
@ 2016-02-18 14:57 ` Shawn Guo
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2016-02-18 14:57 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Feb 14, 2016 at 09:30:06AM +0100, Dirk Behme wrote:
> On 14.02.2016 09:18, Shawn Guo wrote:
> >On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:
> >>On 12.02.2016 15:16, Russell King - ARM Linux wrote:
> >>>On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
> >>>>All the generic L2 cache handling code is encapsulated by a
> >>>>check if the L2 cache is enabled. If it's enabled already, the code
> >>>>is skipped.
> >>>>
> >>>>For the i.MX6 specific L2 cache handling we missed this check.
> >>>>Add it.
> >>>
> >>>What's the reasoning behind this? The prefetch register is writable
> >>>while the L2 cache is enabled, unlike the auxiliary control register.
> >>
> >> From an internal log I have the following info:
> >>
> >>The write to the L2-Cache controller from non-secure world causes an
> >>imprecise
> >>external abort. If Linux runs from normal world the cache controller
> >>is already
> >>enabled and thus no configuration is needed by Linux.
> >
> >Dirk,
> >
> >Do you have a real use case of this, i.e. running Linux on i.MX6 in
> >non-secure world?
>
>
> Yes, in a scenario where one of the cores runs a RTOS.
Can you please reword the commit log to have the above non-secure world
user story mentioned in there?
Shawn
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-02-12 7:11 [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled Dirk Behme
2016-02-12 14:16 ` Russell King - ARM Linux
2016-02-12 15:51 ` Dirk Behme
2016-02-14 8:18 ` Shawn Guo
2016-02-14 8:30 ` Dirk Behme
2016-02-18 14:57 ` Shawn Guo
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