From: shannon.zhao@linaro.org (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v12 03/21] KVM: ARM64: Add offset defines for PMU registers
Date: Tue, 23 Feb 2016 17:29:01 +0800 [thread overview]
Message-ID: <56CC265D.9000406@linaro.org> (raw)
In-Reply-To: <56CBBA06.4040902@huawei.com>
On 2016/2/23 9:46, Shannon Zhao wrote:
>
> On 2016/2/23 1:51, Marc Zyngier wrote:
>> > On 22/02/16 09:37, Shannon Zhao wrote:
>>> >> From: Shannon Zhao <shannon.zhao@linaro.org>
>>> >>
>>> >> We are about to trap and emulate accesses to each PMU register
>>> >> individually. This adds the context offsets for the AArch64 PMU
>>> >> registers.
>>> >>
>>> >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>> >> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
>>> >> Reviewed-by: Andrew Jones <drjones@redhat.com>
>>> >> ---
>>> >> arch/arm64/include/asm/kvm_host.h | 15 +++++++++++++++
>>> >> 1 file changed, 15 insertions(+)
>>> >>
>>> >> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
>>> >> index 6f0241f..6bab7fb 100644
>>> >> --- a/arch/arm64/include/asm/kvm_host.h
>>> >> +++ b/arch/arm64/include/asm/kvm_host.h
>>> >> @@ -115,6 +115,21 @@ enum vcpu_sysreg {
>>> >> MDSCR_EL1, /* Monitor Debug System Control Register */
>>> >> MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
>>> >>
>>> >> + /* Performance Monitors Registers */
>>> >> + PMCR_EL0, /* Control Register */
>>> >> + PMOVSSET_EL0, /* Overflow Flag Status Set Register */
>>> >> + PMSELR_EL0, /* Event Counter Selection Register */
>>> >> + PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
>>> >> + PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
>>> >> + PMCCNTR_EL0, /* Cycle Counter Register */
>>> >> + PMEVTYPER0_EL0, /* Event Type Register (0-30) */
>>> >> + PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
>>> >> + PMCCFILTR_EL0, /* Cycle Count Filter Register */
>>> >> + PMCNTENSET_EL0, /* Count Enable Set Register */
>>> >> + PMINTENSET_EL1, /* Interrupt Enable Set Register */
>>> >> + PMUSERENR_EL0, /* User Enable Register */
>>> >> + PMSWINC_EL0, /* Software Increment Register */
>>> >> +
>> >
>> > I've just noticed a rather fundamental issue with this: this makes it
>> > impossible to bisect the whole series.
>> >
> Ah, sorry. Will fix this.
>
I've fixed this problem and pushed this series to below place. You can
fetch it from there.
https://git.linaro.org/people/shannon.zhao/linux-mainline.git/shortlog/refs/heads/KVM_ARM64_PMU_v13
Thanks,
--
Shannon
next prev parent reply other threads:[~2016-02-23 9:29 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-22 9:37 [PATCH v12 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 01/21] ARM64: Move PMU register related defines to asm/perf_event.h Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-02-22 17:51 ` Marc Zyngier
2016-02-23 1:46 ` Shannon Zhao
2016-02-23 8:33 ` Marc Zyngier
2016-02-23 9:29 ` Shannon Zhao [this message]
2016-02-22 9:37 ` [PATCH v12 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-02-23 17:42 ` Marc Zyngier
2016-02-24 1:27 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-02-23 14:14 ` Marc Zyngier
2016-02-23 14:52 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
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