From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v12 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
Date: Wed, 24 Feb 2016 09:27:43 +0800 [thread overview]
Message-ID: <56CD070F.7070603@huawei.com> (raw)
In-Reply-To: <56CC9A12.6040001@arm.com>
On 2016/2/24 1:42, Marc Zyngier wrote:
> Hi Shannon,
>
> Still picking up on details...
>
> On 22/02/16 09:37, Shannon Zhao wrote:
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> When we use tools like perf on host, perf passes the event type and the
>> id of this event type category to kernel, then kernel will map them to
>> hardware event number and write this number to PMU PMEVTYPER<n>_EL0
>> register. When getting the event number in KVM, directly use raw event
>> type to create a perf_event for it.
>>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> arch/arm64/include/asm/perf_event.h | 2 +
>> arch/arm64/kvm/Makefile | 1 +
>> include/kvm/arm_pmu.h | 12 ++++
>> virt/kvm/arm/pmu.c | 122 ++++++++++++++++++++++++++++++++++++
>> 4 files changed, 137 insertions(+)
>> create mode 100644 virt/kvm/arm/pmu.c
>>
>> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
>> index 5c77ef8..867140d 100644
>> --- a/arch/arm64/include/asm/perf_event.h
>> +++ b/arch/arm64/include/asm/perf_event.h
>> @@ -29,6 +29,8 @@
>> #define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
>> #define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
>> #define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
>> +/* Determines which bit of PMCCNTR_EL0 generates an overflow */
>> +#define ARMV8_PMU_PMCR_LC (1 << 6)
>
> nit: this #define is only being used in patch #14. Consider moving it
> there...
>
Sure, thanks!
--
Shannon
next prev parent reply other threads:[~2016-02-24 1:27 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-22 9:37 [PATCH v12 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 01/21] ARM64: Move PMU register related defines to asm/perf_event.h Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-02-22 17:51 ` Marc Zyngier
2016-02-23 1:46 ` Shannon Zhao
2016-02-23 8:33 ` Marc Zyngier
2016-02-23 9:29 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-02-23 17:42 ` Marc Zyngier
2016-02-24 1:27 ` Shannon Zhao [this message]
2016-02-22 9:37 ` [PATCH v12 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-02-23 14:14 ` Marc Zyngier
2016-02-23 14:52 ` Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-02-22 9:37 ` [PATCH v12 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56CD070F.7070603@huawei.com \
--to=zhaoshenglong@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).