From: caesar.upstream@gmail.com (Caesar Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
Date: Fri, 18 Mar 2016 14:56:05 +0800 [thread overview]
Message-ID: <56EBA685.4070508@gmail.com> (raw)
In-Reply-To: <1455534654-1966-1-git-send-email-ykk@rock-chips.com>
? 2016?02?15? 19:10, Yakir Yang ??:
> RK3288 need some special registers setting, we can separate
> them out by the dev_type of plat_data.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
> ---
> Changes in v14: None
> Changes in v13: None
> Changes in v12: None
> Changes in v11: None
> Changes in v10: None
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Fix compile failed dut to phy_pd_addr variable misspell error
>
> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
> 2 files changed, 60 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 3858df5..1e24b37 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -15,6 +15,8 @@
> #include <linux/delay.h>
> #include <linux/gpio.h>
>
> +#include <drm/bridge/analogix_dp.h>
> +
> #include "analogix_dp_core.h"
> #include "analogix_dp_reg.h"
>
> @@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
> reg = SEL_24M | TX_DVDD_BIT_1_0625V;
> writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
>
> + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
> + writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
> + writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
> + writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
> + writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
> + writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
> + }
> +
In general, I will say what's mean for the number.
Okay that's the rk3288 special registers setting.
> reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
> writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
>
> @@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
> bool enable)
> {
> u32 reg;
> + u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
> +
> + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
> + phy_pd_addr = ANALOGIX_DP_PD;
>
> switch (block) {
> case AUX_BLOCK:
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg |= AUX_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg &= ~AUX_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> }
> break;
> case CH0_BLOCK:
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg |= CH0_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg &= ~CH0_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> }
> break;
> case CH1_BLOCK:
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg |= CH1_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg &= ~CH1_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> }
> break;
> case CH2_BLOCK:
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg |= CH2_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg &= ~CH2_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> }
> break;
> case CH3_BLOCK:
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg |= CH3_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg &= ~CH3_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> }
> break;
> case ANALOG_TOTAL:
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg |= DP_PHY_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> + reg = readl(dp->reg_base + phy_pd_addr);
> reg &= ~DP_PHY_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> }
> break;
> case POWER_ALL:
> if (enable) {
> reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
> CH1_PD | CH0_PD;
> - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(reg, dp->reg_base + phy_pd_addr);
> } else {
> - writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
> + writel(0x00, dp->reg_base + phy_pd_addr);
> }
> break;
> default:
> @@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
> analogix_dp_reset_aux(dp);
>
> /* Disable AUX transaction H/W retry */
> - reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
> - AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
> + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
> + AUX_HW_RETRY_COUNT_SEL(3) |
> + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> + else
> + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
> + AUX_HW_RETRY_COUNT_SEL(0) |
> + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
>
> /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> index 738db4c..337912b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> @@ -22,6 +22,14 @@
> #define ANALOGIX_DP_VIDEO_CTL_8 0x3C
> #define ANALOGIX_DP_VIDEO_CTL_10 0x44
>
> +#define ANALOGIX_DP_PLL_REG_1 0xfc
> +#define ANALOGIX_DP_PLL_REG_2 0x9e4
> +#define ANALOGIX_DP_PLL_REG_3 0x9e8
> +#define ANALOGIX_DP_PLL_REG_4 0x9ec
> +#define ANALOGIX_DP_PLL_REG_5 0xa00
> +
> +#define ANALOGIX_DP_PD 0x12c
> +
> #define ANALOGIX_DP_LANE_MAP 0x35C
>
> #define ANALOGIX_DP_ANALOG_CTL_1 0x370
> @@ -154,6 +162,10 @@
> #define VSYNC_POLARITY_CFG (0x1 << 1)
> #define HSYNC_POLARITY_CFG (0x1 << 0)
>
> +/* ANALOGIX_DP_PLL_REG_1 */
> +#define REF_CLK_24M (0x1 << 1)
> +#define REF_CLK_27M (0x0 << 1)
> +
> /* ANALOGIX_DP_LANE_MAP */
> #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
> #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
--
Thanks,
Caesar
next prev parent reply other threads:[~2016-03-18 6:56 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
2016-02-15 11:09 ` [PATCH v14 02/17] drm/exynos: dp: rename implementation specific driver part Yakir Yang
2016-02-15 11:09 ` [PATCH v14 03/17] drm: bridge: analogix/dp: rename register constants Yakir Yang
2016-02-15 11:09 ` [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2016-03-17 21:48 ` Heiko Stübner
2016-03-17 21:50 ` [PATCH v14.1 " Heiko Stübner
2016-02-15 11:10 ` [PATCH v14 05/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2016-02-15 11:10 ` [PATCH v14 06/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2016-02-15 11:10 ` [PATCH v14 07/17] dt-bindings: add document for analogix display port driver Yakir Yang
2016-02-15 11:10 ` [PATCH v14 08/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2016-02-15 11:10 ` [PATCH v14 09/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2016-03-17 21:51 ` [PATCH v14.1 " Heiko Stübner
2016-03-18 6:45 ` Caesar Wang
2016-03-23 1:08 ` [PATCH v14 " Mark yao
2016-02-15 11:10 ` [PATCH v14 10/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2016-02-15 11:10 ` [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2016-03-18 6:56 ` Caesar Wang [this message]
2016-02-15 11:11 ` [PATCH v14 12/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2016-02-15 11:11 ` [PATCH v14 13/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2016-02-15 11:11 ` [PATCH v14 14/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2016-02-15 11:11 ` [PATCH v14 15/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2016-02-15 11:11 ` [PATCH v14 16/17] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time Yakir Yang
2016-02-15 11:11 ` [PATCH v14 17/17] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time Yakir Yang
2016-03-18 6:41 ` [PATCH v14 0/17] Add Analogix Core Display Port Driver Caesar Wang
2016-03-18 22:53 ` Doug Anderson
2016-03-22 19:19 ` Javier Martinez Canillas
2016-03-22 22:12 ` Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver] Heiko Stübner
2016-03-22 22:44 ` Inki Dae
2016-03-22 22:52 ` Heiko Stübner
2016-03-22 23:09 ` Inki Dae
2016-03-22 23:39 ` Russell King - ARM Linux
2016-03-22 23:54 ` Inki Dae
2016-03-23 0:08 ` Russell King - ARM Linux
2016-03-23 0:41 ` Dave Airlie
2016-03-23 1:08 ` Mark yao
2016-03-23 15:49 ` Thierry Reding
2016-03-24 11:10 ` Yakir Yang
2016-03-24 13:01 ` [PATCH v14 0/17] Add Analogix Core Display Port Driver Heiko Stübner
[not found] ` <1455534576-1486-1-git-send-email-ykk@rock-chips.com>
2016-03-30 20:32 ` [v14, 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Guenter Roeck
2016-03-31 9:56 ` Thierry Reding
2016-03-31 16:02 ` Doug Anderson
2016-04-05 2:15 ` Yakir Yang
2016-03-31 15:57 ` Doug Anderson
2016-04-05 1:49 ` Yakir Yang
[not found] ` <1811552.qvsCm7GUs1@diego>
2016-06-07 17:06 ` [PATCH v14.1 " Javier Martinez Canillas
2016-06-08 1:28 ` Yakir Yang
2016-06-08 7:44 ` Marc Zyngier
2016-06-08 10:53 ` Yakir Yang
2016-06-08 14:19 ` Javier Martinez Canillas
2016-03-31 10:15 ` [PATCH v14 0/17] Add Analogix Core Display Port Driver Daniel Vetter
2016-03-31 10:22 ` Thierry Reding
2016-04-05 2:06 ` Yakir Yang
2016-07-29 8:38 ` Tomeu Vizoso
2016-08-01 1:49 ` Yakir Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56EBA685.4070508@gmail.com \
--to=caesar.upstream@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).