From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support
Date: Fri, 22 Apr 2016 08:43:16 +0100 [thread overview]
Message-ID: <5719D614.1080400@arm.com> (raw)
In-Reply-To: <CADRPPNRU=qy34p4hzYvzBPrt2uabSQfc0Xdd8K5v5B_JW01QJA@mail.gmail.com>
On 22/04/16 06:33, Leo Li wrote:
> On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On Mon, 7 Mar 2016 11:36:22 +0800
>> Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
>>
>>> Some kind of NXP Layerscape SoC provides a MSI
>>> implementation which uses two SCFG registers MSIIR and
>>> MSIR to support 32 MSI interrupts for each PCIe controller.
>>> The patch is to support it.
>>>
>>> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>>
>> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>> The DT binding still needs an Ack from the DT maintainers though (cc'd).
>
> Marc,
>
> Who will be responsible to pick this driver? I see you are also one
> of the maintainers for irqchip. Can you pick up the driver? The
> binding has already gotten ACKed by the device tree maintainer.
Can you point me to this Ack? I can't see any trace of it in my Inbox.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-04-22 7:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 3:36 [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Minghuan Lian
2016-03-07 3:36 ` [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Minghuan Lian
2016-03-07 9:50 ` Marc Zyngier
2016-04-22 5:33 ` Leo Li
2016-04-22 7:43 ` Marc Zyngier [this message]
2016-04-22 7:53 ` Minghuan Lian
2016-04-22 7:58 ` Marc Zyngier
2016-03-23 9:18 ` Alexander Stein
2016-03-23 10:50 ` Minghuan Lian
[not found] ` <56F27914.3080908@arm.com>
2016-03-23 11:19 ` Alexander Stein
2016-03-09 8:57 ` [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Minghuan Lian
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