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Thu, 16 Jul 2020 00:24:59 -0700 (PDT) Subject: Re: [PATCH v4 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 To: Robin Murphy , will@kernel.org, joro@8bytes.org, gregory.clement@bootlin.com, robh+dt@kernel.org, hannah@marvell.com References: <20200715070649.18733-1-tn@semihalf.com> <20200715070649.18733-3-tn@semihalf.com> <793ede4d-79e9-3615-9da1-57cfe1a44c4d@arm.com> From: Tomasz Nowicki Message-ID: <5728f570-b3e5-63fe-9d59-768831943fef@semihalf.com> Date: Thu, 16 Jul 2020 09:24:58 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <793ede4d-79e9-3615-9da1-57cfe1a44c4d@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_032503_618938_9A5E6850 X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, nadavh@marvell.com, iommu@lists.linux-foundation.org, mw@semihalf.com, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 15.07.2020 12:32, Robin Murphy wrote: > On 2020-07-15 08:06, Tomasz Nowicki wrote: >> From: Hanna Hawa >> >> Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to >> ARM SMMUv2 registers. >> >> Provide implementation relevant hooks: >> - split the writeq/readq to two accesses of writel/readl. >> - mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format (but >> only AARCH32_L) since with AArch64 format 32 bits access is not >> supported. >> >> Note that most 64-bit registers like TTBRn can be accessed as two 32-bit >> halves without issue, and AArch32 format ensures that the register writes >> which must be atomic (for TLBI etc.) need only be 32-bit. > > Thanks Tomasz, this has ended up as clean as I'd hoped it could, and > there's still room to come back and play more complicated games later if > a real need for AARCH64_64K at stage 2 crops up. Based on your implementation infrastructure rework, indeed the code looks much cleaner :) > > Reviewed-by: Robin Murphy > Thanks! Tomasz _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel