* [PATCH 1/3] Documentation: Binding docs for bcm11351 enable method
2016-04-28 17:59 [PATCH 0/3] Fixup Broadcom CPU enable method Chris Brand
@ 2016-04-28 17:59 ` Chris Brand
2016-04-28 17:59 ` [PATCH 2/3] arm: dts: fix use of " Chris Brand
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Chris Brand @ 2016-04-28 17:59 UTC (permalink / raw)
To: linux-arm-kernel
Commit 84320e1a635fcf90cff4185f029ce9e31bf1d4a7
("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the
"secondary-boot-reg" property from the "cpus" node to the individual "cpu"
nodes but negelected to update brcm,bcm11351-cpu-method.txt to match.
bcm11351-cpu-method was apparently never added to the list of methods in
bindings/arm/cpus.txt.
bindings/arm/cpus.txt states that "enable-method" should be a property of
the "cpu" node rather than the "cpus" node.
This patch rectifies these two omissions and one inconsistency.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
---
.../devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt | 6 +++---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
index 8240c023e202..e3f996920403 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
@@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
The enable method is specified by defining the following required
-properties in the "cpus" device tree node:
+properties in the "cpu" device tree node:
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <...>;
@@ -19,8 +19,6 @@ Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
cpu0: cpu at 0 {
device_type = "cpu";
@@ -32,5 +30,7 @@ Example:
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ enable-method = "brcm,bcm11351-cpu-method";
+ secondary-boot-reg = <0x3500417c>;
};
};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index ccc62f145306..953350f085c9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -194,6 +194,7 @@ nodes to be present and contain the properties described below.
"allwinner,sun8i-a23"
"arm,psci"
"arm,realview-smp"
+ "brcm,bcm11351-cpu-method"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] arm: dts: fix use of bcm11351 enable method
2016-04-28 17:59 [PATCH 0/3] Fixup Broadcom CPU enable method Chris Brand
2016-04-28 17:59 ` [PATCH 1/3] Documentation: Binding docs for bcm11351 " Chris Brand
@ 2016-04-28 17:59 ` Chris Brand
2016-04-28 17:59 ` [PATCH 3/3] arm: modify Broadcom CPU " Chris Brand
2016-05-03 21:45 ` [PATCH 0/3] Fixup " Florian Fainelli
3 siblings, 0 replies; 5+ messages in thread
From: Chris Brand @ 2016-04-28 17:59 UTC (permalink / raw)
To: linux-arm-kernel
bindings/arm/cpus.txt states that "enable-method" should be a
property of the "cpu" node rather than the "cpus" node.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
---
arch/arm/boot/dts/bcm11351.dtsi | 2 +-
arch/arm/boot/dts/bcm21664.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 3dc7a8cc5812..18045c38bcf1 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -30,7 +30,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
cpu0: cpu at 0 {
device_type = "cpu";
@@ -41,6 +40,7 @@
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
reg = <1>;
};
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 3f525be28fd0..6dde95f21cef 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -30,7 +30,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "brcm,bcm11351-cpu-method";
cpu0: cpu at 0 {
device_type = "cpu";
@@ -41,6 +40,7 @@
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x35004178>;
reg = <1>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] arm: modify Broadcom CPU enable method
2016-04-28 17:59 [PATCH 0/3] Fixup Broadcom CPU enable method Chris Brand
2016-04-28 17:59 ` [PATCH 1/3] Documentation: Binding docs for bcm11351 " Chris Brand
2016-04-28 17:59 ` [PATCH 2/3] arm: dts: fix use of " Chris Brand
@ 2016-04-28 17:59 ` Chris Brand
2016-05-03 21:45 ` [PATCH 0/3] Fixup " Florian Fainelli
3 siblings, 0 replies; 5+ messages in thread
From: Chris Brand @ 2016-04-28 17:59 UTC (permalink / raw)
To: linux-arm-kernel
Commit 84320e1a635fcf90cff4185f029ce9e31bf1d4a7
("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the
"secondary-boot-reg" property from the "cpus" node to the individual "cpu"
nodes but negelected to actually support multiple "secondary-boot-reg"
properties.
This patchset rectifies that omission. Note that the behaviour is changed
slightly in that the "secondary-boot-reg" property is now read in
smp_boot_secondary() rather than smp_prepare_cpus(). This means that any
omissions will now only be reported when and if the cpu in question is being
brought up. It also means that an omission for one cpu will not force
uniprocessor mode.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
---
arch/arm/mach-bcm/platsmp.c | 116 ++++++++++++++------------------------------
1 file changed, 37 insertions(+), 79 deletions(-)
diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
index cfae9c71fb74..5e53cf2fc052 100644
--- a/arch/arm/mach-bcm/platsmp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -37,9 +37,6 @@
#define OF_SECONDARY_BOOT "secondary-boot-reg"
#define MPIDR_CPUID_BITMASK 0x3
-/* I/O address of register used to coordinate secondary core startup */
-static u32 secondary_boot_addr;
-
/*
* Enable the Cortex A9 Snoop Control Unit
*
@@ -81,20 +78,40 @@ static int __init scu_a9_enable(void)
return 0;
}
-static int nsp_write_lut(void)
+static u32 secondary_boot_addr_for(unsigned int cpu)
+{
+ u32 secondary_boot_addr = 0;
+ struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
+
+ if (!cpu_node) {
+ pr_err("Failed to find device tree node for CPU%u\n", cpu);
+ return 0;
+ }
+
+ if (of_property_read_u32(cpu_node,
+ OF_SECONDARY_BOOT,
+ &secondary_boot_addr))
+ pr_err("required secondary boot register not specified for CPU%u\n",
+ cpu);
+
+ of_node_put(cpu_node);
+
+ return secondary_boot_addr;
+}
+
+static int nsp_write_lut(unsigned int cpu)
{
void __iomem *sku_rom_lut;
phys_addr_t secondary_startup_phy;
+ const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
- if (!secondary_boot_addr) {
- pr_warn("required secondary boot register not specified\n");
+ if (!secondary_boot_addr)
return -EINVAL;
- }
sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
- sizeof(secondary_boot_addr));
+ sizeof(phys_addr_t));
if (!sku_rom_lut) {
- pr_warn("unable to ioremap SKU-ROM LUT register\n");
+ pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
return -ENOMEM;
}
@@ -113,70 +130,12 @@ static int nsp_write_lut(void)
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
- static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
- struct device_node *cpus_node = NULL;
- struct device_node *cpu_node = NULL;
- int ret;
-
- /*
- * This function is only called via smp_ops->smp_prepare_cpu().
- * That only happens if a "/cpus" device tree node exists
- * and has an "enable-method" property that selects the SMP
- * operations defined herein.
- */
- cpus_node = of_find_node_by_path("/cpus");
- if (!cpus_node)
- return;
-
- for_each_child_of_node(cpus_node, cpu_node) {
- u32 cpuid;
-
- if (of_node_cmp(cpu_node->type, "cpu"))
- continue;
-
- if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
- pr_debug("%s: missing reg property\n",
- cpu_node->full_name);
- ret = -ENOENT;
- goto out;
- }
-
- /*
- * "secondary-boot-reg" property should be defined only
- * for secondary cpu
- */
- if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
- /*
- * Our secondary enable method requires a
- * "secondary-boot-reg" property to specify a register
- * address used to request the ROM code boot a secondary
- * core. If we have any trouble getting this we fall
- * back to uniprocessor mode.
- */
- if (of_property_read_u32(cpu_node,
- OF_SECONDARY_BOOT,
- &secondary_boot_addr)) {
- pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
- cpu_node->name);
- ret = -ENOENT;
- goto out;
- }
- }
- }
-
- /*
- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
- * returned, the SoC reported a uniprocessor configuration.
- * We bail on any other error.
- */
- ret = scu_a9_enable();
-out:
- of_node_put(cpu_node);
- of_node_put(cpus_node);
+ const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
- if (ret) {
+ /* Enable the SCU on Cortex A9 based SoCs */
+ if (scu_a9_enable()) {
/* Update the CPU present map to reflect uniprocessor mode */
- pr_warn("disabling SMP\n");
+ pr_warn("failed to enable A9 SCU - disabling SMP\n");
init_cpu_present(&only_cpu_0);
}
}
@@ -207,6 +166,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
u32 cpu_id;
u32 boot_val;
bool timeout = false;
+ const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
cpu_id = cpu_logical_map(cpu);
if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
@@ -214,13 +174,11 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -EINVAL;
}
- if (!secondary_boot_addr) {
- pr_err("required secondary boot register not specified\n");
+ if (!secondary_boot_addr)
return -EINVAL;
- }
- boot_reg = ioremap_nocache(
- (phys_addr_t)secondary_boot_addr, sizeof(u32));
+ boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
+ sizeof(phys_addr_t));
if (!boot_reg) {
pr_err("unable to map boot register for cpu %u\n", cpu_id);
return -ENOMEM;
@@ -263,7 +221,7 @@ static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
* After wake up, secondary core branches to the startup
* address programmed at SKU ROM LUT location.
*/
- ret = nsp_write_lut();
+ ret = nsp_write_lut(cpu);
if (ret) {
pr_err("unable to write startup addr to SKU ROM LUT\n");
goto out;
@@ -276,12 +234,12 @@ out:
return ret;
}
-static const struct smp_operations bcm_smp_ops __initconst = {
+static const struct smp_operations kona_smp_ops __initconst = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
.smp_boot_secondary = kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
- &bcm_smp_ops);
+ &kona_smp_ops);
static const struct smp_operations nsp_smp_ops __initconst = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 0/3] Fixup Broadcom CPU enable method
2016-04-28 17:59 [PATCH 0/3] Fixup Broadcom CPU enable method Chris Brand
` (2 preceding siblings ...)
2016-04-28 17:59 ` [PATCH 3/3] arm: modify Broadcom CPU " Chris Brand
@ 2016-05-03 21:45 ` Florian Fainelli
3 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2016-05-03 21:45 UTC (permalink / raw)
To: linux-arm-kernel
On 28/04/16 10:59, Chris Brand wrote:
> This is preparation for supporting the quad-core BCM23550 chip.
>
> Documentation/devicetree/bindings/arm/cpus.txt states that "enable-method"
> should be a property of the "cpu" node rather than the "cpus" node.
>
> Commit 84320e1a635fcf90cff4185f029ce9e31bf1d4a7
> ("ARM: BCM: Clean up SMP support for Broadcom Kona") moved the
> "secondary-boot-reg" property from the "cpus" node to the individual "cpu"
> nodes but negelected to actually support multiple "secondary-boot-reg"
> properties.
>
> This patchset moves the enable-method property to the correct place,
> adds the missing enable-method to the binding documentation, and actually
> supports setting the "enable-method" property on multiple CPU nodes.
>
> Without this change, "secondary-boot-reg" on even-numbered CPUs is ignored,
> and the value specified on the last odd-numbered CPU to be processed
> overrides any earlier values.
>
> Behaviour is slightly changed by this patchset, in that the
> "secondary-boot-reg" property is only examined when the CPU is being enabled.
> This means that the omission of that property will be reported slightly later,
> or never if the CPU in question is never brought online. It also means that
> the omission in one CPU has no effect on other CPUs, whereas previously
> omitting it from one CPU would force the system into single-core mode.
Series applied to devicetree/next, thanks Chris!
--
Florian
^ permalink raw reply [flat|nested] 5+ messages in thread