[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU

[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU

[Krzysztof Kozlowski]

Hi,

Patchset adds necessary clocks, reorganizes existing stuff and finally
adds Odroid XU support.

Merging strategy
================
Complicated! The clock dt-bindings and driver changes can go to clock
tree. However there are three DTS patches in the middle.
a. This has to go in before adding "fin_pll_new" to clock driver:
   - [PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver

b. This should go in before renaming "fin_pll_new" back to original name:
   - [PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock
   - [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410

The order of patches in the patchset is really how it should go in
to reduce any bisectability glitches.


Changes since v1
================
1. A lot of new patches.
2. Removed some TODO notes (eMMC 4.5 so no RCLK pin).
3. New clocks, more reorganization.
4. New common DTSI: exynos54xx.dtsi. I know, it is getting more
   and more complicated but this might help removing duplications
   and keeping everything under control.


Best regards,
Krzysztof


Krzysztof Kozlowski (22):
  dt-bindings: clock: Add license and reformat Exynos5410 clock IDs
  dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410
  ARM: dts: exynos: Add fin_pll node for clock driver
  clk: samsung: exynos5410: Provide fin_pll external fixed clock
  ARM: dts: exynos: Switch MCT node to a new fin_pll clock
  ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410
  clk: samsung: exynos5410: Rename fin_pll from temporary to regular
    name
  clk: samsung: exynos5410: Add serial3, USB and PWM clocks
  ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl
    nodes
  ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels
  ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card
  ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI
  ARM: dts: exynos: Move common nodes to exynos5.dtsi
  ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in
    exynos5410.dtsi
  ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
  ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
  ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi
  ARM: dts: exynos: Enable UART3 on Exynos5410
  ARM: dts: exynos: MCT is not an interrupt controller and extend length
    of iomap
  ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
  ARM: dts: exynos: Add USB to Exynos5410
  ARM: dts: exynos: Add initial support for Odroid XU board

 .../bindings/arm/samsung/samsung-boards.txt        |    1 +
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/exynos5.dtsi                     |  171 +-
 arch/arm/boot/dts/exynos5250-snow-common.dtsi      |    2 +-
 arch/arm/boot/dts/exynos5250.dtsi                  | 1718 +++++++++--------
 arch/arm/boot/dts/exynos5410-odroidxu.dts          |  166 ++
 arch/arm/boot/dts/exynos5410-pinctrl.dtsi          |   77 +
 arch/arm/boot/dts/exynos5410-smdk5410.dts          |   16 +-
 arch/arm/boot/dts/exynos5410.dtsi                  |  204 +-
 arch/arm/boot/dts/exynos5420-pinctrl.dtsi          |   12 +-
 arch/arm/boot/dts/exynos5420.dtsi                  | 1981 ++++++++++----------
 arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts    |   35 +-
 arch/arm/boot/dts/exynos5422-odroidxu3.dts         |   35 +-
 arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi    |   50 +
 arch/arm/boot/dts/exynos54xx.dtsi                  |  142 ++
 drivers/clk/samsung/clk-exynos5410.c               |   52 +
 include/dt-bindings/clock/exynos5410.h             |   64 +-
 17 files changed, 2519 insertions(+), 2208 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts
 create mode 100644 arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
 create mode 100644 arch/arm/boot/dts/exynos54xx.dtsi

-- 
2.5.0

[PATCH v2 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs

[Krzysztof Kozlowski]

Add license and copyrights (file introduced in 2014) to header with
Exynos5410 clock IDs. Additionally reformat it to improve readability.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 include/dt-bindings/clock/exynos5410.h | 54 ++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 22 deletions(-)

diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 9b180f032e2d..213f19e02870 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -1,33 +1,43 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5421 clock controller.
+*/
+
 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
 
 /* core clocks */
-#define CLK_FIN_PLL 1
-#define CLK_FOUT_APLL 2
-#define CLK_FOUT_CPLL 3
-#define CLK_FOUT_MPLL 4
-#define CLK_FOUT_BPLL 5
-#define CLK_FOUT_KPLL 6
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_MPLL		4
+#define CLK_FOUT_BPLL		5
+#define CLK_FOUT_KPLL		6
 
 /* gate for special clocks (sclk) */
-#define CLK_SCLK_UART0 128
-#define CLK_SCLK_UART1 129
-#define CLK_SCLK_UART2 130
-#define CLK_SCLK_UART3 131
-#define CLK_SCLK_MMC0 132
-#define CLK_SCLK_MMC1 133
-#define CLK_SCLK_MMC2 134
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
 
 /* gate clocks */
-#define CLK_UART0 257
-#define CLK_UART1 258
-#define CLK_UART2 259
-#define CLK_UART3 260
-#define CLK_MCT 315
-#define CLK_MMC0 351
-#define CLK_MMC1 352
-#define CLK_MMC2 353
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_UART3		260
+#define CLK_MCT			315
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
 
-#define CLK_NR_CLKS 512
+#define CLK_NR_CLKS		512
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
-- 
2.5.0

[PATCH v2 02/22] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410

[Krzysztof Kozlowski]

Add IDs for PWM and USB clocks to Exynos5410. Use the same number as for
Exynos5420 just in case in future these drivers were merged.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 include/dt-bindings/clock/exynos5410.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 213f19e02870..34c8e96987a1 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2016 Krzysztof Kozlowski
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -27,16 +28,25 @@
 #define CLK_SCLK_MMC0		132
 #define CLK_SCLK_MMC1		133
 #define CLK_SCLK_MMC2		134
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_PWM		155
 
 /* gate clocks */
 #define CLK_UART0		257
 #define CLK_UART1		258
 #define CLK_UART2		259
 #define CLK_UART3		260
+#define CLK_PWM			279
 #define CLK_MCT			315
 #define CLK_MMC0		351
 #define CLK_MMC1		352
 #define CLK_MMC2		353
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
 
 #define CLK_NR_CLKS		512
 
-- 
2.5.0

[PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver

[Krzysztof Kozlowski]

For consistency between Exynos5410 and Exynos542x/5800 switch to similar
way of defining fin_pll/oscclk. Add a node early, before implementing
this in driver to preserve bisectability.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410-smdk5410.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 0f6429e1b75c..d7d658deeff4 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -31,6 +31,13 @@
 		#clock-cells = <0>;
 	};
 
+	fixed-rate-clocks {
+		oscclk {
+			compatible = "samsung,exynos5420-oscclk";
+			clock-frequency = <24000000>;
+		};
+	};
+
 	firmware at 02037000 {
 		compatible = "samsung,secure-firmware";
 		reg = <0x02037000 0x1000>;
-- 
2.5.0

[PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock

[Krzysztof Kozlowski]

Just like clock driver for Exynos542x/5800, provide the fixed clock here
so the clock bindings and their consumers would be consistent and
similar.

However a clock named "fin_pll" is already provided by generic
fixed-clock and it is both referenced in the clock driver (by name) and
in DT (by phandle). To make the transition smooth, first introduce the
new external fixed clock here under temporary, different name and switch
internal users to it.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/clk/samsung/clk-exynos5410.c | 42 +++++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d5d5dcabc4a9..35f2cb36f7ef 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -59,23 +59,29 @@ enum exynos5410_plls {
 };
 
 /* list of all parent clocks */
-PNAME(apll_p)		= { "fin_pll", "fout_apll", };
-PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
-PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
-PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
-PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
+PNAME(apll_p)		= { "fin_pll_new", "fout_apll", };
+PNAME(bpll_p)		= { "fin_pll_new", "fout_bpll", };
+PNAME(cpll_p)		= { "fin_pll_new", "fout_cpll" };
+PNAME(mpll_p)		= { "fin_pll_new", "fout_mpll", };
+PNAME(kpll_p)		= { "fin_pll_new", "fout_kpll", };
 
 PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
 PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
 
-PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
-PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
+PNAME(mpll_user_p)	= { "fin_pll_new", "sclk_mpll", };
+PNAME(bpll_user_p)	= { "fin_pll_new", "sclk_bpll", };
 PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
 
-PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
+PNAME(group2_p)		= { "fin_pll_new", "fin_pll_new", "none", "none",
 			"none", "none", "sclk_mpll_bpll",
 			 "none", "none", "sclk_cpll" };
 
+/* fixed rate clocks generated outside the soc */
+static struct samsung_fixed_rate_clock
+		exynos5x_fixed_rate_ext_clks[] __initdata = {
+	FRATE(CLK_FIN_PLL, "fin_pll_new", NULL, 0, 0),
+};
+
 static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
 	MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
@@ -168,18 +174,24 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 };
 
 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
-	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll_new", APLL_LOCK,
 		APLL_CON0, NULL),
-	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll_new", CPLL_LOCK,
 		CPLL_CON0, NULL),
-	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll_new", MPLL_LOCK,
 		MPLL_CON0, NULL),
-	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll_new", BPLL_LOCK,
 		BPLL_CON0, NULL),
-	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll_new", KPLL_LOCK,
 		KPLL_CON0, NULL),
 };
 
+/* Same as in Exynos5420 */
+static const struct of_device_id ext_clk_match[] __initconst = {
+	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
+	{ },
+};
+
 /* register exynos5410 clocks */
 static void __init exynos5410_clk_init(struct device_node *np)
 {
@@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np)
 
 	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
 
+	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
+			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
+			ext_clk_match);
+
 	samsung_clk_register_pll(ctx, exynos5410_plls,
 			ARRAY_SIZE(exynos5410_plls), reg_base);
 
-- 
2.5.0

[PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock

[Krzysztof Kozlowski]

The clk-exynos5410 driver now provides the "fin_pll" external fixed
clock. Switch the Multi-Core Timer to this clock.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 7a56aec2c5ba..233149abfb62 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -125,7 +125,7 @@
 			interrupts = <0>, <1>, <2>, <3>,
 				<4>, <5>, <6>, <7>,
 				<8>, <9>, <10>, <11>;
-			clocks = <&fin_pll>, <&clock CLK_MCT>;
+			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 			clock-names = "fin_pll", "mct";
 
 			interrupt_map: interrupt-map {
-- 
2.5.0

[PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410

[Krzysztof Kozlowski]

All "fin_pll" clock users are switched to the new one, provided by
Exynos5410 clock driver. Remove old DT node.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410-smdk5410.dts | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index d7d658deeff4..377a679b454b 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -24,13 +24,6 @@
 		bootargs = "console=ttySAC2,115200";
 	};
 
-	fin_pll: xxti {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "fin_pll";
-		#clock-cells = <0>;
-	};
-
 	fixed-rate-clocks {
 		oscclk {
 			compatible = "samsung,exynos5420-oscclk";
-- 
2.5.0

[PATCH v2 07/22] clk: samsung: exynos5410: Rename fin_pll from temporary to regular name

[Krzysztof Kozlowski]

For smooth transition of fin_pll to clk-exynos5410.c from fixed-clock
driver, initially it was named "fin_pll_new". Fix this here.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/clk/samsung/clk-exynos5410.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index 35f2cb36f7ef..a7d714435307 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -59,27 +59,27 @@ enum exynos5410_plls {
 };
 
 /* list of all parent clocks */
-PNAME(apll_p)		= { "fin_pll_new", "fout_apll", };
-PNAME(bpll_p)		= { "fin_pll_new", "fout_bpll", };
-PNAME(cpll_p)		= { "fin_pll_new", "fout_cpll" };
-PNAME(mpll_p)		= { "fin_pll_new", "fout_mpll", };
-PNAME(kpll_p)		= { "fin_pll_new", "fout_kpll", };
+PNAME(apll_p)		= { "fin_pll", "fout_apll", };
+PNAME(bpll_p)		= { "fin_pll", "fout_bpll", };
+PNAME(cpll_p)		= { "fin_pll", "fout_cpll" };
+PNAME(mpll_p)		= { "fin_pll", "fout_mpll", };
+PNAME(kpll_p)		= { "fin_pll", "fout_kpll", };
 
 PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };
 PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
 
-PNAME(mpll_user_p)	= { "fin_pll_new", "sclk_mpll", };
-PNAME(bpll_user_p)	= { "fin_pll_new", "sclk_bpll", };
+PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
+PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
 PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
 
-PNAME(group2_p)		= { "fin_pll_new", "fin_pll_new", "none", "none",
+PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
 			"none", "none", "sclk_mpll_bpll",
 			 "none", "none", "sclk_cpll" };
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock
 		exynos5x_fixed_rate_ext_clks[] __initdata = {
-	FRATE(CLK_FIN_PLL, "fin_pll_new", NULL, 0, 0),
+	FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
 };
 
 static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
@@ -174,15 +174,15 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 };
 
 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
-	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll_new", APLL_LOCK,
+	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
 		APLL_CON0, NULL),
-	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll_new", CPLL_LOCK,
+	[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
 		CPLL_CON0, NULL),
-	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll_new", MPLL_LOCK,
+	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
 		MPLL_CON0, NULL),
-	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll_new", BPLL_LOCK,
+	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
 		BPLL_CON0, NULL),
-	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll_new", KPLL_LOCK,
+	[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
 		KPLL_CON0, NULL),
 };
 
-- 
2.5.0

[PATCH v2 08/22] clk: samsung: exynos5410: Add serial3, USB and PWM clocks

[Krzysztof Kozlowski]

Just like other Exynos5 family SoCs, this one has four UARTs. Add
missing UART3 clocks to the Exynso5410 clock driver.

Add clocks for USB and PWM.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/clk/samsung/clk-exynos5410.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index a7d714435307..40775f678f02 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -33,9 +33,11 @@
 #define SRC_CPERI1		0x4204
 #define DIV_TOP0		0x10510
 #define DIV_TOP1		0x10514
+#define DIV_FSYS0		0x10548
 #define DIV_FSYS1		0x1054c
 #define DIV_FSYS2		0x10550
 #define DIV_PERIC0		0x10558
+#define DIV_PERIC3		0x10564
 #define SRC_TOP0		0x10210
 #define SRC_TOP1		0x10214
 #define SRC_TOP2		0x10218
@@ -44,6 +46,8 @@
 #define SRC_MASK_FSYS		0x10340
 #define SRC_MASK_PERIC0		0x10350
 #define GATE_BUS_FSYS0		0x10740
+#define GATE_TOP_SCLK_FSYS	0x10840
+#define GATE_TOP_SCLK_PERIC	0x10850
 #define GATE_IP_FSYS		0x10944
 #define GATE_IP_PERIC		0x10950
 #define GATE_IP_PERIS		0x10960
@@ -71,6 +75,7 @@ PNAME(mout_kfc_p)	= { "mout_kpll", "sclk_mpll", };
 PNAME(mpll_user_p)	= { "fin_pll", "sclk_mpll", };
 PNAME(bpll_user_p)	= { "fin_pll", "sclk_bpll", };
 PNAME(mpll_bpll_p)	= { "sclk_mpll_muxed", "sclk_bpll_muxed", };
+PNAME(sclk_mpll_bpll_p)	= { "sclk_mpll_bpll", "fin_pll", };
 
 PNAME(group2_p)		= { "fin_pll", "fin_pll", "none", "none",
 			"none", "none", "sclk_mpll_bpll",
@@ -102,10 +107,14 @@ static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
 	MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
 	MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
 	MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
+	MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
+	MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
 
 	MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
 	MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
 	MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
+	MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
+	MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
 
 	MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
 	MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
@@ -127,6 +136,11 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 	DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
 	DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
 
+	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
+	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
+
 	DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 	DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
 	DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
@@ -143,6 +157,8 @@ static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
 	DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
 	DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
 
+	DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+
 	DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
 	DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
 };
@@ -161,9 +177,23 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 	GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
 	GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
 
+	GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
+	     GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
+	     GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
+	     GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
+	     GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
+	     GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
+
 	GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
 	GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
 	GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+	GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+	GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
 
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
 			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
@@ -171,6 +201,12 @@ static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
 			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
 			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
+			SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
 };
 
 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
-- 
2.5.0

[PATCH v2 09/22] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes

[Krzysztof Kozlowski]

The 'sd0_rclk' was put in the middle of SD1 nodes. Remove the confusion.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index 130563b2ca95..14beb7e07323 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -193,17 +193,17 @@
 		samsung,pin-drv = <3>;
 	};
 
-	sd1_clk: sd1-clk {
-		samsung,pins = "gpc1-0";
+	sd0_rclk: sd0-rclk {
+		samsung,pins = "gpc0-7";
 		samsung,pin-function = <2>;
-		samsung,pin-pud = <0>;
+		samsung,pin-pud = <1>;
 		samsung,pin-drv = <3>;
 	};
 
-	sd0_rclk: sd0-rclk {
-		samsung,pins = "gpc0-7";
+	sd1_clk: sd1-clk {
+		samsung,pins = "gpc1-0";
 		samsung,pin-function = <2>;
-		samsung,pin-pud = <1>;
+		samsung,pin-pud = <0>;
 		samsung,pin-drv = <3>;
 	};
 
-- 
2.5.0

[PATCH v2 10/22] ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels

[Krzysztof Kozlowski]

Fro consistency lowercase node labels are used.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 233149abfb62..58d3844ef923 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -35,28 +35,28 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		CPU0: cpu at 0 {
+		cpu0: cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 			clock-frequency = <1600000000>;
 		};
 
-		CPU1: cpu at 1 {
+		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 			clock-frequency = <1600000000>;
 		};
 
-		CPU2: cpu at 2 {
+		cpu2: cpu at 2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x2>;
 			clock-frequency = <1600000000>;
 		};
 
-		CPU3: cpu at 3 {
+		cpu3: cpu at 3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x3>;
-- 
2.5.0

[PATCH v2 11/22] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card

[Krzysztof Kozlowski]

Configure the pinctrl for MMC0 (eMMC) and MMC2 (microSD card).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 77 +++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index f9aa6bb55464..72fc659d0637 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -277,6 +277,83 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
+
+	sd0_clk: sd0-clk {
+		samsung,pins = "gpc0-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_cmd: sd0-cmd {
+		samsung,pins = "gpc0-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_cd: sd0-cd {
+		samsung,pins = "gpc0-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus1: sd0-bus-width1 {
+		samsung,pins = "gpc0-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus4: sd0-bus-width4 {
+		samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd0_bus8: sd0-bus-width8 {
+		samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_clk: sd2-clk {
+		samsung,pins = "gpc2-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_cmd: sd2-cmd {
+		samsung,pins = "gpc2-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_cd: sd2-cd {
+		samsung,pins = "gpc2-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_bus1: sd2-bus-width1 {
+		samsung,pins = "gpc2-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_bus4: sd2-bus-width4 {
+		samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
 };
 
 &pinctrl_1 {
-- 
2.5.0

[PATCH v2 12/22] ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI

[Krzysztof Kozlowski]

The LED nodes can be shared between Odroid XU3, XU3-Lite and XU (not yet
added) thus removing duplication.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 35 +----------------
 arch/arm/boot/dts/exynos5422-odroidxu3.dts      | 35 +----------------
 arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 50 +++++++++++++++++++++++++
 3 files changed, 52 insertions(+), 68 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 2ae1cf41dcb6..03fa88c45426 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -14,44 +14,11 @@
 /dts-v1/;
 #include "exynos5422-odroidxu3-common.dtsi"
 #include "exynos5422-odroidxu3-audio.dtsi"
+#include "exynos54xx-odroidxu-leds.dtsi"
 
 / {
 	model = "Hardkernel Odroid XU3 Lite";
 	compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
-
-	pwmleds {
-		compatible = "pwm-leds";
-
-		greenled {
-			label = "green:mmc0";
-			pwms = <&pwm 1 2000000 0>;
-			pwm-names = "pwm1";
-			/*
-			 * Green LED is much brighter than the others
-			 * so limit its max brightness
-			 */
-			max_brightness = <127>;
-			linux,default-trigger = "mmc0";
-		};
-
-		blueled {
-			label = "blue:heartbeat";
-			pwms = <&pwm 2 2000000 0>;
-			pwm-names = "pwm2";
-			max_brightness = <255>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-
-	gpioleds {
-		compatible = "gpio-leds";
-		redled {
-			label = "red:microSD";
-			gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			linux,default-trigger = "mmc1";
-		};
-	};
 };
 
 &pwm {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 432406db85de..9ed6564acfb0 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -13,44 +13,11 @@
 /dts-v1/;
 #include "exynos5422-odroidxu3-common.dtsi"
 #include "exynos5422-odroidxu3-audio.dtsi"
+#include "exynos54xx-odroidxu-leds.dtsi"
 
 / {
 	model = "Hardkernel Odroid XU3";
 	compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
-
-	pwmleds {
-		compatible = "pwm-leds";
-
-		greenled {
-			label = "green:mmc0";
-			pwms = <&pwm 1 2000000 0>;
-			pwm-names = "pwm1";
-			/*
-			 * Green LED is much brighter than the others
-			 * so limit its max brightness
-			 */
-			max_brightness = <127>;
-			linux,default-trigger = "mmc0";
-		};
-
-		blueled {
-			label = "blue:heartbeat";
-			pwms = <&pwm 2 2000000 0>;
-			pwm-names = "pwm2";
-			max_brightness = <255>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-
-	gpioleds {
-		compatible = "gpio-leds";
-		redled {
-			label = "red:microSD";
-			gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			linux,default-trigger = "mmc1";
-		};
-	};
 };
 
 &i2c_0 {
diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
new file mode 100644
index 000000000000..0ed30206625c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Hardkernel Odroid XU/XU3 LED device tree source
+ *
+ * Copyright (c) 2015,2016 Krzysztof Kozlowski
+ * Copyright (c) 2014 Collabora Ltd.
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+
+		greenled {
+			label = "green:mmc0";
+			pwms = <&pwm 1 2000000 0>;
+			pwm-names = "pwm1";
+			/*
+			 * Green LED is much brighter than the others
+			 * so limit its max brightness
+			 */
+			max_brightness = <127>;
+			linux,default-trigger = "mmc0";
+		};
+
+		blueled {
+			label = "blue:heartbeat";
+			pwms = <&pwm 2 2000000 0>;
+			pwm-names = "pwm2";
+			max_brightness = <255>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	gpioleds {
+		compatible = "gpio-leds";
+		redled {
+			label = "red:microSD";
+			gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mmc1";
+		};
+	};
+};
-- 
2.5.0

[PATCH v2 13/22] ARM: dts: exynos: Move common nodes to exynos5.dtsi

[Krzysztof Kozlowski]

Exynos5420 and Exynos5250 share some nodes: the PWM and syscon
(sysreg_system_controller). Move them to parent DTSI to avoid
duplication.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5.dtsi    | 12 ++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi | 19 +++++--------------
 arch/arm/boot/dts/exynos5420.dtsi | 19 +++++--------------
 3 files changed, 22 insertions(+), 28 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index d5c0f18a4223..fe901152f3ea 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -63,6 +63,11 @@
 		interrupts = <1 9 0xf04>;
 	};
 
+	sysreg_system_controller: syscon at 10050000 {
+		compatible = "samsung,exynos5-sysreg", "syscon";
+		reg = <0x10050000 0x5000>;
+	};
+
 	serial_0: serial at 12C00000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x12C00000 0x100>;
@@ -87,6 +92,13 @@
 		interrupts = <0 54 0>;
 	};
 
+	pwm: pwm at 12DD0000 {
+		compatible = "samsung,exynos4210-pwm";
+		reg = <0x12DD0000 0x100>;
+		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+		#pwm-cells = <3>;
+	};
+
 	rtc: rtc at 101E0000 {
 		compatible = "samsung,s3c6410-rtc";
 		reg = <0x101E0000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index c7158b2fb213..6762faaf12a8 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -235,11 +235,6 @@
 		interrupt-parent = <&gic>;
 	};
 
-	sysreg_system_controller: syscon at 10050000 {
-		compatible = "samsung,exynos5-sysreg", "syscon";
-		reg = <0x10050000 0x5000>;
-	};
-
 	watchdog at 101D0000 {
 		compatible = "samsung,exynos5250-wdt";
 		reg = <0x101D0000 0x100>;
@@ -662,15 +657,6 @@
 		samsung,pmureg-phandle = <&pmu_system_controller>;
 	};
 
-	pwm: pwm at 12dd0000 {
-		compatible = "samsung,exynos4210-pwm";
-		reg = <0x12dd0000 0x100>;
-		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
-		#pwm-cells = <3>;
-		clocks = <&clock CLK_PWM>;
-		clock-names = "timers";
-	};
-
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -1070,6 +1056,11 @@
 	iommus = <&sysmmu_fimd1>;
 };
 
+&pwm {
+	clocks = <&clock CLK_PWM>;
+	clock-names = "timers";
+};
+
 &rtc {
 	clocks = <&clock CLK_RTC>;
 	clock-names = "rtc";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 4c8523471c65..f7322d87095f 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -542,15 +542,6 @@
 		status = "disabled";
 	};
 
-	pwm: pwm at 12dd0000 {
-		compatible = "samsung,exynos4210-pwm";
-		reg = <0x12dd0000 0x100>;
-		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
-		#pwm-cells = <3>;
-		clocks = <&clock CLK_PWM>;
-		clock-names = "timers";
-	};
-
 	dp_phy: dp-video-phy {
 		compatible = "samsung,exynos5420-dp-video-phy";
 		samsung,pmu-syscon = <&pmu_system_controller>;
@@ -823,11 +814,6 @@
 		interrupt-parent = <&gic>;
 	};
 
-	sysreg_system_controller: syscon at 10050000 {
-		compatible = "samsung,exynos5-sysreg", "syscon";
-		reg = <0x10050000 0x5000>;
-	};
-
 	tmu_cpu0: tmu at 10060000 {
 		compatible = "samsung,exynos5420-tmu";
 		reg = <0x10060000 0x100>;
@@ -1207,6 +1193,11 @@
 	iommu-names = "m0", "m1";
 };
 
+&pwm {
+	clocks = <&clock CLK_PWM>;
+	clock-names = "timers";
+};
+
 &rtc {
 	clocks = <&clock CLK_RTC>;
 	clock-names = "rtc";
-- 
2.5.0

[PATCH v2 14/22] ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi

[Krzysztof Kozlowski]

Add 'sromc' label to SROM memory controller in common exynos5.dtsi so it
can be referenced by inheriting DTSI.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index fe901152f3ea..7c83dc6ef972 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -31,7 +31,7 @@
 		reg = <0x10000000 0x100>;
 	};
 
-	memory-controller at 12250000 {
+	sromc: memory-controller at 12250000 {
 		compatible = "samsung,exynos4210-srom";
 		reg = <0x12250000 0x14>;
 	};
-- 
2.5.0

[PATCH v2 15/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow

[Krzysztof Kozlowski]

The i2c-arbitrator node in exynos5250-snow-common used absolute path to
reference other node (the i2c parent). Use phandle instead, because the
depth of the other node may be changed (like moving it under 'soc'
node).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5250-snow-common.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index ddfe1f558c10..419d59da1751 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -61,7 +61,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		i2c-parent = <&{/i2c@12CA0000}>;
+		i2c-parent = <&i2c_4>;
 
 		our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
 		their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
-- 
2.5.0

[PATCH v2 17/22] ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi

[Krzysztof Kozlowski]

The exynos5.dtsi is used for common nodes shared between Exynos5250 and
Exynos542x. Since Exynos5410 is very similar to Exynos5420 it can
include the common file as well to remove duplication and make
everything more consistent.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410-smdk5410.dts |   6 +-
 arch/arm/boot/dts/exynos5410.dtsi         | 103 ++++++++++--------------------
 2 files changed, 35 insertions(+), 74 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 377a679b454b..501f776f327d 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -102,14 +102,14 @@
 	};
 };
 
-&uart0 {
+&serial_0 {
 	status = "okay";
 };
 
-&uart1 {
+&serial_1 {
 	status = "okay";
 };
 
-&uart2 {
+&serial_2 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 58d3844ef923..c0540eb76271 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include "skeleton.dtsi"
+#include "exynos5.dtsi"
 #include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos5410.h>
 
@@ -26,9 +27,6 @@
 		pinctrl1 = &pinctrl_1;
 		pinctrl2 = &pinctrl_2;
 		pinctrl3 = &pinctrl_3;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
 	};
 
 	cpus {
@@ -70,49 +68,6 @@
 		#size-cells = <1>;
 		ranges;
 
-		combiner: interrupt-controller at 10440000 {
-			compatible = "samsung,exynos4210-combiner";
-			#interrupt-cells = <2>;
-			interrupt-controller;
-			samsung,combiner-nr = <32>;
-			reg = <0x10440000 0x1000>;
-			interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-					<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-					<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-					<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-					<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
-		};
-
-		gic: interrupt-controller at 10481000 {
-			compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg =	<0x10481000 0x1000>,
-				<0x10482000 0x1000>,
-				<0x10484000 0x2000>,
-				<0x10486000 0x2000>;
-			interrupts = <1 9 0xf04>;
-		};
-
-		chipid at 10000000 {
-			compatible = "samsung,exynos4210-chipid";
-			reg = <0x10000000 0x100>;
-		};
-
-		sromc: memory-controller at 12250000 {
-			compatible = "samsung,exynos4210-srom";
-			reg = <0x12250000 0x14>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-			ranges = <0 0 0x04000000 0x20000
-				  1 0 0x05000000 0x20000
-				  2 0 0x06000000 0x20000
-				  3 0 0x07000000 0x20000>;
-		};
-
 		pmu_system_controller: system-controller at 10040000 {
 			compatible = "samsung,exynos5410-pmu", "syscon";
 			reg = <0x10040000 0x5000>;
@@ -236,34 +191,40 @@
 			reg = <0x03860000 0x1000>;
 			interrupts = <0 47 0>;
 		};
+	};
+};
 
-		uart0: serial at 12C00000 {
-			compatible = "samsung,exynos4210-uart";
-			reg = <0x12C00000 0x100>;
-			interrupts = <0 51 0>;
-			clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
-			clock-names = "uart", "clk_uart_baud0";
-			status = "disabled";
-		};
+&pwm {
+	clocks = <&clock CLK_PWM>;
+	clock-names = "timers";
+};
 
-		uart1: serial at 12C10000 {
-			compatible = "samsung,exynos4210-uart";
-			reg = <0x12C10000 0x100>;
-			interrupts = <0 52 0>;
-			clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
-			clock-names = "uart", "clk_uart_baud0";
-			status = "disabled";
-		};
+&serial_0 {
+	clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+	clock-names = "uart", "clk_uart_baud0";
+};
 
-		uart2: serial at 12C20000 {
-			compatible = "samsung,exynos4210-uart";
-			reg = <0x12C20000 0x100>;
-			interrupts = <0 53 0>;
-			clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
-			clock-names = "uart", "clk_uart_baud0";
-			status = "disabled";
-		};
-	};
+&serial_1 {
+	clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+	clock-names = "uart", "clk_uart_baud0";
+};
+
+&serial_2 {
+	clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+	clock-names = "uart", "clk_uart_baud0";
+};
+
+&serial_3 {
+	status = "disabled";
+};
+
+&sromc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x04000000 0x20000
+		  1 0 0x05000000 0x20000
+		  2 0 0x06000000 0x20000
+		  3 0 0x07000000 0x20000>;
 };
 
 #include "exynos5410-pinctrl.dtsi"
-- 
2.5.0

[PATCH v2 18/22] ARM: dts: exynos: Enable UART3 on Exynos5410

[Krzysztof Kozlowski]

Just like other Exynos5 family SoCs, this one has four UARTs. Configure
clocks for UART3 and enable it.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index c0540eb76271..62dc3b4aef93 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -215,7 +215,8 @@
 };
 
 &serial_3 {
-	status = "disabled";
+	clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+	clock-names = "uart", "clk_uart_baud0";
 };
 
 &sromc {
-- 
2.5.0

[PATCH v2 19/22] ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap

[Krzysztof Kozlowski]

Multi-Core Timer generates interrupts but it is not really an interrupt
controller so remove the "interrupt-controller" and "interrupt-cells"
properties. Additionally extend the length of mapped memory to cover all
registers (last SFR is at 0x0A40).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5420.dtsi | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 3114cd6fb5d1..ac39e3b8b0e1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -267,9 +267,7 @@
 
 		mct: mct at 101C0000 {
 			compatible = "samsung,exynos4210-mct";
-			reg = <0x101C0000 0x800>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
+			reg = <0x101C0000 0xB00>;
 			interrupt-parent = <&mct_map>;
 			interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 					<8>, <9>, <10>, <11>;
-- 
2.5.0

[PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI

[Krzysztof Kozlowski]

The Exynos5410/542x/5800 are very similar designs. Create new new
DTSI with common nodes to remove DTS duplication. Although currently
only MCT and SysRAM are shared but in future more nodes will be added to
common file.

The patch should not have functional impact.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos5410.dtsi | 55 ++++---------------------------
 arch/arm/boot/dts/exynos5420.dtsi | 54 ++++---------------------------
 arch/arm/boot/dts/exynos54xx.dtsi | 68 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 80 insertions(+), 97 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos54xx.dtsi

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 62dc3b4aef93..850343d3c2af 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -13,8 +13,7 @@
  * published by the Free Software Foundation.
  */
 
-#include "skeleton.dtsi"
-#include "exynos5.dtsi"
+#include "exynos54xx.dtsi"
 #include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos5410.h>
 
@@ -73,53 +72,6 @@
 			reg = <0x10040000 0x5000>;
 		};
 
-		mct: mct at 101C0000 {
-			compatible = "samsung,exynos4210-mct";
-			reg = <0x101C0000 0xB00>;
-			interrupt-parent = <&interrupt_map>;
-			interrupts = <0>, <1>, <2>, <3>,
-				<4>, <5>, <6>, <7>,
-				<8>, <9>, <10>, <11>;
-			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
-			clock-names = "fin_pll", "mct";
-
-			interrupt_map: interrupt-map {
-				#interrupt-cells = <1>;
-				#address-cells = <0>;
-				#size-cells = <0>;
-				interrupt-map = <0 &combiner 23 3>,
-						<1 &combiner 23 4>,
-						<2 &combiner 25 2>,
-						<3 &combiner 25 3>,
-						<4 &gic 0 120 0>,
-						<5 &gic 0 121 0>,
-						<6 &gic 0 122 0>,
-						<7 &gic 0 123 0>,
-						<8 &gic 0 128 0>,
-						<9 &gic 0 129 0>,
-						<10 &gic 0 130 0>,
-						<11 &gic 0 131 0>;
-			};
-		};
-
-		sysram at 02020000 {
-			compatible = "mmio-sram";
-			reg = <0x02020000 0x54000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x02020000 0x54000>;
-
-			smp-sysram at 0 {
-				compatible = "samsung,exynos4210-sysram";
-				reg = <0x0 0x1000>;
-			};
-
-			smp-sysram at 53000 {
-				compatible = "samsung,exynos4210-sysram-ns";
-				reg = <0x53000 0x1000>;
-			};
-		};
-
 		clock: clock-controller at 10010000 {
 			compatible = "samsung,exynos5410-clock";
 			reg = <0x10010000 0x30000>;
@@ -194,6 +146,11 @@
 	};
 };
 
+&mct {
+	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+	clock-names = "fin_pll", "mct";
+};
+
 &pwm {
 	clocks = <&clock CLK_PWM>;
 	clock-names = "timers";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ac39e3b8b0e1..750571f838f2 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -13,9 +13,8 @@
  * published by the Free Software Foundation.
  */
 
+#include "exynos54xx.dtsi"
 #include <dt-bindings/clock/exynos5420.h>
-#include "exynos5.dtsi"
-
 #include <dt-bindings/clock/exynos-audss-clk.h>
 
 / {
@@ -185,24 +184,6 @@
 			};
 		};
 
-		sysram at 02020000 {
-			compatible = "mmio-sram";
-			reg = <0x02020000 0x54000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x02020000 0x54000>;
-
-			smp-sysram at 0 {
-				compatible = "samsung,exynos4210-sysram";
-				reg = <0x0 0x1000>;
-			};
-
-			smp-sysram at 53000 {
-				compatible = "samsung,exynos4210-sysram-ns";
-				reg = <0x53000 0x1000>;
-			};
-		};
-
 		clock: clock-controller at 10010000 {
 			compatible = "samsung,exynos5420-clock";
 			reg = <0x10010000 0x30000>;
@@ -265,34 +246,6 @@
 			status = "disabled";
 		};
 
-		mct: mct at 101C0000 {
-			compatible = "samsung,exynos4210-mct";
-			reg = <0x101C0000 0xB00>;
-			interrupt-parent = <&mct_map>;
-			interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
-					<8>, <9>, <10>, <11>;
-			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
-			clock-names = "fin_pll", "mct";
-
-			mct_map: mct-map {
-				#interrupt-cells = <1>;
-				#address-cells = <0>;
-				#size-cells = <0>;
-				interrupt-map = <0 &combiner 23 3>,
-						<1 &combiner 23 4>,
-						<2 &combiner 25 2>,
-						<3 &combiner 25 3>,
-						<4 &gic 0 120 0>,
-						<5 &gic 0 121 0>,
-						<6 &gic 0 122 0>,
-						<7 &gic 0 123 0>,
-						<8 &gic 0 128 0>,
-						<9 &gic 0 129 0>,
-						<10 &gic 0 130 0>,
-						<11 &gic 0 131 0>;
-			};
-		};
-
 		gsc_pd: power-domain at 10044000 {
 			compatible = "samsung,exynos4210-pd";
 			reg = <0x10044000 0x20>;
@@ -1194,6 +1147,11 @@
 	iommu-names = "m0", "m1";
 };
 
+&mct {
+	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+	clock-names = "fin_pll", "mct";
+};
+
 &pwm {
 	clocks = <&clock CLK_PWM>;
 	clock-names = "timers";
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
new file mode 100644
index 000000000000..9ce625bd79c1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Samsung's Exynos54xx SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
+ * Exynos 54xx SoCs should include this file and customize it further
+ * (e.g. with clocks).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include "exynos5.dtsi"
+
+/ {
+	compatible = "samsung,exynos5";
+
+	soc: soc {
+		sysram at 02020000 {
+			compatible = "mmio-sram";
+			reg = <0x02020000 0x54000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x02020000 0x54000>;
+
+			smp-sysram at 0 {
+				compatible = "samsung,exynos4210-sysram";
+				reg = <0x0 0x1000>;
+			};
+
+			smp-sysram at 53000 {
+				compatible = "samsung,exynos4210-sysram-ns";
+				reg = <0x53000 0x1000>;
+			};
+		};
+
+		mct: mct at 101C0000 {
+			compatible = "samsung,exynos4210-mct";
+			reg = <0x101C0000 0xB00>;
+			interrupt-parent = <&mct_map>;
+			interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+					<8>, <9>, <10>, <11>;
+
+			mct_map: mct-map {
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = <0 &combiner 23 3>,
+						<1 &combiner 23 4>,
+						<2 &combiner 25 2>,
+						<3 &combiner 25 3>,
+						<4 &gic 0 120 0>,
+						<5 &gic 0 121 0>,
+						<6 &gic 0 122 0>,
+						<7 &gic 0 123 0>,
+						<8 &gic 0 128 0>,
+						<9 &gic 0 129 0>,
+						<10 &gic 0 130 0>,
+						<11 &gic 0 131 0>;
+			};
+		};
+	};
+};
-- 
2.5.0

[PATCH v2 21/22] ARM: dts: exynos: Add USB to Exynos5410

[Krzysztof Kozlowski]

Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to
exynos54xx.dtsi common for entire family. For Exynos542x/5800 this
should not have functional impact but for Exynos5410 this effectively
adds USB support.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

---

TODO: lack of regulator causes errors:
	usb usb4-port1: over-current condition
?
---
 arch/arm/boot/dts/exynos5410.dtsi |  39 ++++++++++++
 arch/arm/boot/dts/exynos5420.dtsi | 131 ++++++++++++--------------------------
 arch/arm/boot/dts/exynos54xx.dtsi |  74 +++++++++++++++++++++
 3 files changed, 152 insertions(+), 92 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 850343d3c2af..dd4d6d752865 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -185,4 +185,43 @@
 		  3 0 0x07000000 0x20000>;
 };
 
+&usbdrd3_0 {
+	clocks = <&clock CLK_USBD300>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+	clocks = <&clock CLK_USBD301>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usbhost2 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usb2_phy {
+	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,sysreg-phandle = <&sysreg_system_controller>;
+	samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5410-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 750571f838f2..ebf1dbec5070 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -829,98 +829,6 @@
 			clock-names = "secss";
 		};
 
-		usbdrd3_0: usb3-0 {
-			compatible = "samsung,exynos5250-dwusb3";
-			clocks = <&clock CLK_USBD300>;
-			clock-names = "usbdrd30";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			usbdrd_dwc3_0: dwc3 at 12000000 {
-				compatible = "snps,dwc3";
-				reg = <0x12000000 0x10000>;
-				interrupts = <0 72 0>;
-				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
-				phy-names = "usb2-phy", "usb3-phy";
-			};
-		};
-
-		usbdrd_phy0: phy at 12100000 {
-			compatible = "samsung,exynos5420-usbdrd-phy";
-			reg = <0x12100000 0x100>;
-			clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-		};
-
-		usbdrd3_1: usb3-1 {
-			compatible = "samsung,exynos5250-dwusb3";
-			clocks = <&clock CLK_USBD301>;
-			clock-names = "usbdrd30";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			usbdrd_dwc3_1: dwc3 at 12400000 {
-				compatible = "snps,dwc3";
-				reg = <0x12400000 0x10000>;
-				interrupts = <0 73 0>;
-				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
-				phy-names = "usb2-phy", "usb3-phy";
-			};
-		};
-
-		usbdrd_phy1: phy at 12500000 {
-			compatible = "samsung,exynos5420-usbdrd-phy";
-			reg = <0x12500000 0x100>;
-			clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-		};
-
-		usbhost2: usb at 12110000 {
-			compatible = "samsung,exynos4210-ehci";
-			reg = <0x12110000 0x100>;
-			interrupts = <0 71 0>;
-
-			clocks = <&clock CLK_USBH20>;
-			clock-names = "usbhost";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			port at 0 {
-				reg = <0>;
-				phys = <&usb2_phy 1>;
-			};
-		};
-
-		usbhost1: usb at 12120000 {
-			compatible = "samsung,exynos4210-ohci";
-			reg = <0x12120000 0x100>;
-			interrupts = <0 71 0>;
-
-			clocks = <&clock CLK_USBH20>;
-			clock-names = "usbhost";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			port at 0 {
-				reg = <0>;
-				phys = <&usb2_phy 1>;
-			};
-		};
-
-		usb2_phy: phy at 12130000 {
-			compatible = "samsung,exynos5250-usb2-phy";
-			reg = <0x12130000 0x100>;
-			clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
-			clock-names = "phy", "ref";
-			#phy-cells = <1>;
-			samsung,sysreg-phandle = <&sysreg_system_controller>;
-			samsung,pmureg-phandle = <&pmu_system_controller>;
-		};
-
 		sysmmu_g2dr: sysmmu at 0x10A60000 {
 			compatible = "samsung,exynos-sysmmu";
 			reg = <0x10A60000 0x1000>;
@@ -1184,4 +1092,43 @@
 	clock-names = "uart", "clk_uart_baud0";
 };
 
+&usbdrd3_0 {
+	clocks = <&clock CLK_USBD300>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+	clocks = <&clock CLK_USBD301>;
+	clock-names = "usbdrd30";
+};
+
+&usbdrd_phy1 {
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+	clock-names = "phy", "ref";
+	samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usbhost2 {
+	clocks = <&clock CLK_USBH20>;
+	clock-names = "usbhost";
+};
+
+&usb2_phy {
+	clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+	clock-names = "phy", "ref";
+	samsung,sysreg-phandle = <&sysreg_system_controller>;
+	samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5420-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9ce625bd79c1..0f3b8735849e 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -64,5 +64,79 @@
 						<11 &gic 0 131 0>;
 			};
 		};
+
+		usbdrd3_0: usb3-0 {
+			compatible = "samsung,exynos5250-dwusb3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbdrd_dwc3_0: dwc3 at 12000000 {
+				compatible = "snps,dwc3";
+				reg = <0x12000000 0x10000>;
+				interrupts = <0 72 0>;
+				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy0: phy at 12100000 {
+			compatible = "samsung,exynos5420-usbdrd-phy";
+			reg = <0x12100000 0x100>;
+			#phy-cells = <1>;
+		};
+
+		usbdrd3_1: usb3-1 {
+			compatible = "samsung,exynos5250-dwusb3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbdrd_dwc3_1: dwc3 at 12400000 {
+				compatible = "snps,dwc3";
+				reg = <0x12400000 0x10000>;
+				interrupts = <0 73 0>;
+				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+			};
+		};
+
+		usbdrd_phy1: phy at 12500000 {
+			compatible = "samsung,exynos5420-usbdrd-phy";
+			reg = <0x12500000 0x100>;
+			#phy-cells = <1>;
+		};
+
+		usbhost2: usb at 12110000 {
+			compatible = "samsung,exynos4210-ehci";
+			reg = <0x12110000 0x100>;
+			interrupts = <0 71 0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port at 0 {
+				reg = <0>;
+				phys = <&usb2_phy 1>;
+			};
+		};
+
+		usbhost1: usb at 12120000 {
+			compatible = "samsung,exynos4210-ohci";
+			reg = <0x12120000 0x100>;
+			interrupts = <0 71 0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port at 0 {
+				reg = <0>;
+				phys = <&usb2_phy 1>;
+			};
+		};
+
+		usb2_phy: phy at 12130000 {
+			compatible = "samsung,exynos5250-usb2-phy";
+			reg = <0x12130000 0x100>;
+			#phy-cells = <1>;
+		};
 	};
 };
-- 
2.5.0

[PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board

[Krzysztof Kozlowski]

The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3
the differences are:
1. Exynos5410 instead of 5422,
2. DisplayPort,
3. Main PMIC: Maxim 77802 instead of S2MPS11,
4. USB3503+LAN9730 instead of integrated LAN9514,
5. eMMC 4.5 instead of eMMC 5.0,

This patch adds initial support for the XU board with working basic
functions, eMMC/SD and USB (including attached ethernet adapter).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 .../bindings/arm/samsung/samsung-boards.txt        |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/exynos5410-odroidxu.dts          | 166 +++++++++++++++++++++
 3 files changed, 168 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts

diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index f5deace2b380..0ea7f14ef294 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -47,6 +47,7 @@ Required root node properties:
 	- "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.
 	- "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.
 	- "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.
+	- "hardkernel,odroid-xu"  - for Exynos5410-based Hardkernel Odroid XU.
 	- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
 	- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
 					 Odroid XU3 Lite board.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5aeb10674370..9ed1c7abedb1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
 	exynos5250-snow-rev5.dtb \
 	exynos5250-spring.dtb \
 	exynos5260-xyref5260.dtb \
+	exynos5410-odroidxu.dtb \
 	exynos5410-smdk5410.dtb \
 	exynos5420-arndale-octa.dtb \
 	exynos5420-peach-pit.dtb \
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
new file mode 100644
index 000000000000..b0cbd53aeea9
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -0,0 +1,166 @@
+/*
+ * Hardkernel Odroid XU3 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "exynos54xx-odroidxu-leds.dtsi"
+
+/ {
+	model = "Hardkernel Odroid XU";
+	compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
+
+	memory {
+		reg = <0x40000000 0x7EA00000>;
+	};
+
+	chosen {
+		linux,stdout-path = &serial_2;
+	};
+
+	/* TODO: these will be the same as in XU3-common file */
+	emmc_pwrseq: pwrseq {
+		pinctrl-0 = <&emmc_nrst_pin>;
+		pinctrl-names = "default";
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
+	};
+
+	fan0: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm 0 20972 0>;
+		cooling-min-state = <0>;
+		cooling-max-state = <3>;
+		#cooling-cells = <2>;
+		cooling-levels = <0 130 170 230>;
+	};
+
+	fixed-rate-clocks {
+		oscclk {
+			compatible = "samsung,exynos5420-oscclk";
+			clock-frequency = <24000000>;
+		};
+	};
+
+	firmware at 02073000 {
+		compatible = "samsung,secure-firmware";
+		reg = <0x02073000 0x1000>;
+	};
+};
+
+/* TODO:
+&i2c_4 {
+	status = "okay";
+
+	ina231 at 40 {
+		compatible = "ti,ina231";
+		reg = <0x40>;
+		shunt-resistor = <10000>;
+	};
+
+	ina231 at 41 {
+		compatible = "ti,ina231";
+		reg = <0x41>;
+		shunt-resistor = <10000>;
+	};
+
+	ina231 at 44 {
+		compatible = "ti,ina231";
+		reg = <0x44>;
+		shunt-resistor = <10000>;
+	};
+
+	ina231 at 45 {
+		compatible = "ti,ina231";
+		reg = <0x45>;
+		shunt-resistor = <10000>;
+	};
+};
+*/
+
+&mmc_0 {
+	status = "okay";
+	mmc-pwrseq = <&emmc_pwrseq>;
+	cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	samsung,dw-mshc-hs400-timing = <0 2>;
+	samsung,read-strobe-delay = <90>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	//vmmc-supply = <&ldo18_reg>; // FIXME
+	//vqmmc-supply = <&ldo3_reg>; // FIXME
+};
+
+&mmc_2 {
+	status = "okay";
+	card-detect-delay = <200>;
+	samsung,dw-mshc-ciu-div = <3>;
+	samsung,dw-mshc-sdr-timing = <0 4>;
+	samsung,dw-mshc-ddr-timing = <0 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	//vmmc-supply = <&ldo19_reg>; // FIXME
+	//vqmmc-supply = <&ldo13_reg>; // Thats gonna be different than XU3 // FIXME
+};
+
+&pinctrl_0 {
+	emmc_nrst_pin: emmc-nrst {
+		samsung,pins = "gpd1-0";
+		samsung,pin-function = <0>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <0>;
+	};
+};
+
+&serial_0 {
+	status = "okay";
+};
+
+&serial_1 {
+	status = "okay";
+};
+
+&serial_2 {
+	status = "okay";
+};
+
+&serial_3 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "peripheral";
+};
+
+&usbdrd3_0 {
+//	vdd33-supply = <&ldo9_reg>;
+//	vdd10-supply = <&ldo11_reg>;
+};
+
+&usbdrd3_1 {
+//	vdd33-supply = <&ldo9_reg>;
+//	vdd10-supply = <&ldo11_reg>;
+};
-- 
2.5.0

[PATCH v2 01/22] dt-bindings: clock: Add license and reformat Exynos5410 clock IDs

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Add license and copyrights (file introduced in 2014) to header with
> Exynos5410 clock IDs. Additionally reformat it to improve readability.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 02/22] dt-bindings: clock: Add PWM and USB clock IDs to Exynos5410

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Add IDs for PWM and USB clocks to Exynos5410. Use the same number as for
> Exynos5420 just in case in future these drivers were merged.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> For consistency between Exynos5410 and Exynos542x/5800 switch to similar
> way of defining fin_pll/oscclk. Add a node early, before implementing
> this in driver to preserve bisectability.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board

[Rob Herring]

On Sun, May 08, 2016 at 09:06:07PM +0200, Krzysztof Kozlowski wrote:
> The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
> from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3
> the differences are:
> 1. Exynos5410 instead of 5422,
> 2. DisplayPort,
> 3. Main PMIC: Maxim 77802 instead of S2MPS11,
> 4. USB3503+LAN9730 instead of integrated LAN9514,
> 5. eMMC 4.5 instead of eMMC 5.0,
> 
> This patch adds initial support for the XU board with working basic
> functions, eMMC/SD and USB (including attached ethernet adapter).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  .../bindings/arm/samsung/samsung-boards.txt        |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/exynos5410-odroidxu.dts          | 166 +++++++++++++++++++++
>  3 files changed, 168 insertions(+)
>  create mode 100644 arch/arm/boot/dts/exynos5410-odroidxu.dts
> 
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index f5deace2b380..0ea7f14ef294 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -47,6 +47,7 @@ Required root node properties:
>  	- "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.
>  	- "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.
>  	- "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.
> +	- "hardkernel,odroid-xu"  - for Exynos5410-based Hardkernel Odroid XU.
>  	- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
>  	- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
>  					 Odroid XU3 Lite board.
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 5aeb10674370..9ed1c7abedb1 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
>  	exynos5250-snow-rev5.dtb \
>  	exynos5250-spring.dtb \
>  	exynos5260-xyref5260.dtb \
> +	exynos5410-odroidxu.dtb \
>  	exynos5410-smdk5410.dtb \
>  	exynos5420-arndale-octa.dtb \
>  	exynos5420-peach-pit.dtb \
> diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
> new file mode 100644
> index 000000000000..b0cbd53aeea9
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
> @@ -0,0 +1,166 @@
> +/*
> + * Hardkernel Odroid XU3 board device tree source
> + *
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + * Copyright (c) 2016 Krzysztof Kozlowski
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos5410.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "exynos54xx-odroidxu-leds.dtsi"
> +
> +/ {
> +	model = "Hardkernel Odroid XU";
> +	compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
> +
> +	memory {
> +		reg = <0x40000000 0x7EA00000>;

lowercase hex please.

With that,

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Just like clock driver for Exynos542x/5800, provide the fixed clock here
> so the clock bindings and their consumers would be consistent and
> similar.
> 
> However a clock named "fin_pll" is already provided by generic
> fixed-clock and it is both referenced in the clock driver (by name) and
> in DT (by phandle). To make the transition smooth, first introduce the
> new external fixed clock here under temporary, different name and switch
> internal users to it.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

[snip]

>  
> +/* Same as in Exynos5420 */
> +static const struct of_device_id ext_clk_match[] __initconst = {
> +	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },

Since using designated initializers, I was about to say that there is no need
to explicitly set .data to 0 since omitted fields are implicitly initialized...

> +	{ },
> +};
> +
>  /* register exynos5410 clocks */
>  static void __init exynos5410_clk_init(struct device_node *np)
>  {
> @@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np)
>  
>  	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
>  
> +	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
> +			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
> +			ext_clk_match);
> +

... but then I noticed that .data is used as exynos5x_fixed_rate_ext_clks
array index in samsung_clk_of_register_fixed_ext(). So makes sense to set
it explicitly to make the intent clear.

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> The clk-exynos5410 driver now provides the "fin_pll" external fixed
> clock. Switch the Multi-Core Timer to this clock.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> All "fin_pll" clock users are switched to the new one, provided by

s/are switched/were switched

> Exynos5410 clock driver. Remove old DT node.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 07/22] clk: samsung: exynos5410: Rename fin_pll from temporary to regular name

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> For smooth transition of fin_pll to clk-exynos5410.c from fixed-clock
> driver, initially it was named "fin_pll_new". Fix this here.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 08/22] clk: samsung: exynos5410: Add serial3, USB and PWM clocks

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Just like other Exynos5 family SoCs, this one has four UARTs. Add
> missing UART3 clocks to the Exynso5410 clock driver.
> 
> Add clocks for USB and PWM.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

I don't have an Exynos5410 SoC user manual to double check all values
but assuming that are correct, the patch looks good to me.

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
 
Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 09/22] ARM: dts: exynos: Re-order alphabetically Exynos5420 SD0/SD1 pinctrl nodes

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> The 'sd0_rclk' was put in the middle of SD1 nodes. Remove the confusion.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 10/22] ARM: dts: exynos: Use lowercase for Exynos5410 CPU node labels

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Fro consistency lowercase node labels are used.
>

s/Fro/For
 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 11/22] ARM: dts: exynos: Configure Exynos5410 pinctrl for eMMC and SD card

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Configure the pinctrl for MMC0 (eMMC) and MMC2 (microSD card).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 12/22] ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> The LED nodes can be shared between Odroid XU3, XU3-Lite and XU (not yet
> added) thus removing duplication.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 13/22] ARM: dts: exynos: Move common nodes to exynos5.dtsi

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Exynos5420 and Exynos5250 share some nodes: the PWM and syscon
> (sysreg_system_controller). Move them to parent DTSI to avoid
> duplication.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

I see that the i2c_[0-3] nodes are also the same in both DTSI. Do you
think that makes sense to also move those to exynos5.dtsi as well?

In any case that can be made as a follow-up, so:

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 14/22] ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> Add 'sromc' label to SROM memory controller in common exynos5.dtsi so it
> can be referenced by inheriting DTSI.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 15/22] ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> The i2c-arbitrator node in exynos5250-snow-common used absolute path to
> reference other node (the i2c parent). Use phandle instead, because the
> depth of the other node may be changed (like moving it under 'soc'
> node).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 16/22] ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> The conventions it to put SoC devices under 'soc' node. In fact other

s/it/is

> our DTSes (like exynos3250.dtsi or exynos5410.dtsi) already follows it.
> Adjust exynos5250 and exynos5420 DTSI to follow this convention. This is
> also necessary for the upcoming change in exynos5410.dtsi to inherit
> from common exynos5.dtsi.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 17/22] ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> The exynos5.dtsi is used for common nodes shared between Exynos5250 and
> Exynos542x. Since Exynos5410 is very similar to Exynos5420 it can
> include the common file as well to remove duplication and make
> everything more consistent.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 18/22] ARM: dts: exynos: Enable UART3 on Exynos5410

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> Just like other Exynos5 family SoCs, this one has four UARTs. Configure
> clocks for UART3 and enable it.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 19/22] ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> Multi-Core Timer generates interrupts but it is not really an interrupt
> controller so remove the "interrupt-controller" and "interrupt-cells"
> properties. Additionally extend the length of mapped memory to cover all
> registers (last SFR is at 0x0A40).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> The Exynos5410/542x/5800 are very similar designs. Create new new

s/new new/a new

> DTSI with common nodes to remove DTS duplication. Although currently
> only MCT and SysRAM are shared but in future more nodes will be added to
> common file.
> 
> The patch should not have functional impact.
> 

A nice way to check this is to diff the disassembled compiled DTBs with
and without the patch and making sure that the resulted DTS is the same.

> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
 
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 21/22] ARM: dts: exynos: Add USB to Exynos5410

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to
> exynos54xx.dtsi common for entire family. For Exynos542x/5800 this
> should not have functional impact but for Exynos5410 this effectively
> adds USB support.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> 

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU

[Stephen Boyd]

On 05/08, Krzysztof Kozlowski wrote:
> 
> Hi,
> 
> Patchset adds necessary clocks, reorganizes existing stuff and finally
> adds Odroid XU support.
> 
> Merging strategy
> ================
> Complicated! The clock dt-bindings and driver changes can go to clock
> tree. However there are three DTS patches in the middle.
> a. This has to go in before adding "fin_pll_new" to clock driver:
>    - [PATCH v2 03/22] ARM: dts: exynos: Add fin_pll node for clock driver
> 
> b. This should go in before renaming "fin_pll_new" back to original name:
>    - [PATCH v2 05/22] ARM: dts: exynos: Switch MCT node to a new fin_pll clock
>    - [PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410
> 
> The order of patches in the patchset is really how it should go in
> to reduce any bisectability glitches.

If you want to just merge them through arm-soc then feel free to
add my Acked-by to the clk driver and clock dt-binding ones.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
> The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
> from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3
> the differences are:
> 1. Exynos5410 instead of 5422,
> 2. DisplayPort,
> 3. Main PMIC: Maxim 77802 instead of S2MPS11,
> 4. USB3503+LAN9730 instead of integrated LAN9514,
> 5. eMMC 4.5 instead of eMMC 5.0,
> 
> This patch adds initial support for the XU board with working basic
> functions, eMMC/SD and USB (including attached ethernet adapter).
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---

This DTS has some TODO's, FIXME's and commented input supplies. Probably
this patch should had been an RFC? or you should mention about these in
the commit message to understand why are there.

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
> 
> Hi,
> 
> Patchset adds necessary clocks, reorganizes existing stuff and finally
> adds Odroid XU support.
> 

Do you have a branch available so I can pull these patches and test in
the Exynos5 boards I've access to?

Thanks a lot and best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU

[Krzysztof Kozlowski]

On 05/10/2016 12:05 AM, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
>>
>> Hi,
>>
>> Patchset adds necessary clocks, reorganizes existing stuff and finally
>> adds Odroid XU support.
>>
> 
> Do you have a branch available so I can pull these patches and test in
> the Exynos5 boards I've access to?

Of course. It sits on my private repo, on Github:
https://github.com/krzk/linux
branch: for-next/odroid-xu-v2

Best regards,
Krzysztof

[PATCH v2 04/22] clk: samsung: exynos5410: Provide fin_pll external fixed clock

[Krzysztof Kozlowski]

On 05/09/2016 10:19 PM, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
>> Just like clock driver for Exynos542x/5800, provide the fixed clock here
>> so the clock bindings and their consumers would be consistent and
>> similar.
>>
>> However a clock named "fin_pll" is already provided by generic
>> fixed-clock and it is both referenced in the clock driver (by name) and
>> in DT (by phandle). To make the transition smooth, first introduce the
>> new external fixed clock here under temporary, different name and switch
>> internal users to it.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
> 
> [snip]
> 
>>  
>> +/* Same as in Exynos5420 */
>> +static const struct of_device_id ext_clk_match[] __initconst = {
>> +	{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
> 
> Since using designated initializers, I was about to say that there is no need
> to explicitly set .data to 0 since omitted fields are implicitly initialized...
> 
>> +	{ },
>> +};
>> +
>>  /* register exynos5410 clocks */
>>  static void __init exynos5410_clk_init(struct device_node *np)
>>  {
>> @@ -192,6 +204,10 @@ static void __init exynos5410_clk_init(struct device_node *np)
>>  
>>  	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
>>  
>> +	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
>> +			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
>> +			ext_clk_match);
>> +
> 
> ... but then I noticed that .data is used as exynos5x_fixed_rate_ext_clks
> array index in samsung_clk_of_register_fixed_ext(). So makes sense to set
> it explicitly to make the intent clear.

Yes, that is the intention here. The '(void *)0' is a hint that clock
needs frequency from DT.

Thanks for review,
Krzysztof

[PATCH v2 06/22] ARM: dts: exynos: Remove old fixed-clock provider on SMDK5410

[Krzysztof Kozlowski]

On 05/09/2016 10:24 PM, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
>> All "fin_pll" clock users are switched to the new one, provided by
> 
> s/are switched/were switched

Thanks for spotting this,
Krzysztof

[PATCH v2 13/22] ARM: dts: exynos: Move common nodes to exynos5.dtsi

[Krzysztof Kozlowski]

On 05/09/2016 11:25 PM, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
>> Exynos5420 and Exynos5250 share some nodes: the PWM and syscon
>> (sysreg_system_controller). Move them to parent DTSI to avoid
>> duplication.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
> 
> I see that the i2c_[0-3] nodes are also the same in both DTSI. Do you
> think that makes sense to also move those to exynos5.dtsi as well?

Thanks, that is a good suggestion. I didn't add the I2C and its children
to Odroid XU yet but probably having the nodes defined won't hurt.
Especially that they are disabled by default.

Best regards,
Krzysztof

> In any case that can be made as a follow-up, so:
> 
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> 
> Best regards,
> 

[PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI

[Krzysztof Kozlowski]

On 05/09/2016 11:53 PM, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
>> The Exynos5410/542x/5800 are very similar designs. Create new new
> 
> s/new new/a new
> 
>> DTSI with common nodes to remove DTS duplication. Although currently
>> only MCT and SysRAM are shared but in future more nodes will be added to
>> common file.
>>
>> The patch should not have functional impact.
>>
> 
> A nice way to check this is to diff the disassembled compiled DTBs with
> and without the patch and making sure that the resulted DTS is the same.

Yes, that is what I've done. Recently there is a tool making that even
easier: dtx_diff.

Best regards,
Krzysztof

[PATCH v2 22/22] ARM: dts: exynos: Add initial support for Odroid XU board

[Krzysztof Kozlowski]

On 05/10/2016 12:02 AM, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
>> The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
>> from Samsung: the Exynos5410. Comparing now to more popular Odroid XU3
>> the differences are:
>> 1. Exynos5410 instead of 5422,
>> 2. DisplayPort,
>> 3. Main PMIC: Maxim 77802 instead of S2MPS11,
>> 4. USB3503+LAN9730 instead of integrated LAN9514,
>> 5. eMMC 4.5 instead of eMMC 5.0,
>>
>> This patch adds initial support for the XU board with working basic
>> functions, eMMC/SD and USB (including attached ethernet adapter).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
> 
> This DTS has some TODO's, FIXME's and commented input supplies. Probably
> this patch should had been an RFC? or you should mention about these in
> the commit message to understand why are there.

I have to clean it up or fix these notes. Actually I was quite surprised
that board worked fine with this basic setup.

Best regards,
Krzysztof

[PATCH v2 20/22] ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/10/2016 01:33 AM, Krzysztof Kozlowski wrote:
> On 05/09/2016 11:53 PM, Javier Martinez Canillas wrote:
>> Hello Krzysztof,
>>
>> On 05/08/2016 03:06 PM, Krzysztof Kozlowski wrote:
>>> The Exynos5410/542x/5800 are very similar designs. Create new new
>>
>> s/new new/a new
>>
>>> DTSI with common nodes to remove DTS duplication. Although currently
>>> only MCT and SysRAM are shared but in future more nodes will be added to
>>> common file.
>>>
>>> The patch should not have functional impact.
>>>
>>
>> A nice way to check this is to diff the disassembled compiled DTBs with
>> and without the patch and making sure that the resulted DTS is the same.
> 
> Yes, that is what I've done. Recently there is a tool making that even
> easier: dtx_diff.
>

I didn't know we had such a tool in mainline now.
Very useful, thanks a lot for the information.
 
> Best regards,
> Krzysztof
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

[PATCH v2 00/22] ARM: dts: exynos: Add initial support for Odroid XU

[Javier Martinez Canillas]

Hello Krzysztof,

On 05/10/2016 01:13 AM, Krzysztof Kozlowski wrote:
> On 05/10/2016 12:05 AM, Javier Martinez Canillas wrote:
>> Hello Krzysztof,
>>
>> On 05/08/2016 03:05 PM, Krzysztof Kozlowski wrote:
>>>
>>> Hi,
>>>
>>> Patchset adds necessary clocks, reorganizes existing stuff and finally
>>> adds Odroid XU support.
>>>
>>
>> Do you have a branch available so I can pull these patches and test in
>> the Exynos5 boards I've access to?
> 
> Of course. It sits on my private repo, on Github:
> https://github.com/krzk/linux
> branch: for-next/odroid-xu-v2
>

Thanks for the information, I'll give a try today.
 
> Best regards,
> Krzysztof
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America