Re: [PATCH 2/5] clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate

Jernej Škrabec
2023-12-19T16:47:37Z

Dne ponedeljek, 18. december 2023 ob 14:35:20 CET je Frank Oltmanns napisal(a):
> The Allwinner A64 manual lists the following constraints for the
> PLL-MIPI clock:
> - M/N >= 3

Same as in previous patch, should be "<=".

Best regards,
Jernej

> - (PLL_VIDEO0)/M >= 24MHz
>
> Use these constraints.
>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index 8951ffc14ff5..c034ac027d1c 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -176,6 +176,8 @@ static struct ccu_nkm pll_mipi_clk = {
> .n = _SUNXI_CCU_MULT(8, 4),
> .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> .m = _SUNXI_CCU_DIV(0, 4),
> + .max_mn_ratio = 3,
> + .parent_wo_nk = 24000000,
> .common = {
> .reg = 0x040,
> .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",