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From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/7] KVM: arm/arm64: vgic-v2: Always resample level interrupts
Date: Mon, 23 May 2016 15:41:42 +0100	[thread overview]
Message-ID: <574316A6.8030305@arm.com> (raw)
In-Reply-To: <20160523141937.GA9625@lvm>

On 23/05/16 15:19, Christoffer Dall wrote:
> On Mon, May 23, 2016 at 01:36:59PM +0100, Marc Zyngier wrote:
>> When reading back from the list registers, we need to perform
>> two actions for level interrupts:
>> 1) clear the soft-pending bit if the interrupt is not pending
>>    anymore *in the list register*
>> 2) resample the line level and propagate it to the pending state
>>
>> But these two actions linked, and we should *always* resample
> 
> were linked?

Indeed.

> 
>> the line level, no matter what state is in the list register.
>> Otherwise, we may end-up injecting spurious interrupts that
>> have been already retired.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  virt/kvm/arm/vgic/vgic-v2.c | 11 +++++++----
>>  1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/virt/kvm/arm/vgic/vgic-v2.c b/virt/kvm/arm/vgic/vgic-v2.c
>> index 8ad42c2..f659af0 100644
>> --- a/virt/kvm/arm/vgic/vgic-v2.c
>> +++ b/virt/kvm/arm/vgic/vgic-v2.c
>> @@ -112,10 +112,13 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
>>  			}
>>  		}
>>  
>> -		/* Clear soft pending state when level IRQs have been acked */
>> -		if (irq->config == VGIC_CONFIG_LEVEL &&
>> -		    !(val & GICH_LR_PENDING_BIT)) {
>> -			irq->soft_pending = false;
>> +		/*
>> +		 * Clear soft pending state when level irqs have been acked.
>> +		 * Always resample the line level.
>> +		 */
>> +		if (irq->config == VGIC_CONFIG_LEVEL) {
>> +			if (!(val & GICH_LR_PENDING_BIT))
>> +				irq->soft_pending = false;
>>  			irq->pending = irq->line_level;
> 
> shouldn't this context line then be:
> 	irq->pending = irq->line_level || irq->soft_pending;  ??

Yes, you're right. The only case we discard the soft-pending bit is when
we know for sure that the interrupt has transitioned from pending to active.

I'll update the two patches and repost once the rest of the series has
been reviewed.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2016-05-23 14:41 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-23 12:36 [PATCH 0/7] vgic fixes for 4.7-rc1 Marc Zyngier
2016-05-23 12:36 ` [PATCH 1/7] KVM: arm/arm64: vgic-v2: Clear all dirty LRs Marc Zyngier
2016-05-23 12:36 ` [PATCH 2/7] KVM: arm/arm64: vgic-v3: " Marc Zyngier
2016-05-23 12:36 ` [PATCH 3/7] KVM: arm/arm64: vgic-v2: Always resample level interrupts Marc Zyngier
2016-05-23 14:19   ` Christoffer Dall
2016-05-23 14:41     ` Marc Zyngier [this message]
2016-05-23 12:37 ` [PATCH 4/7] KVM: arm/arm64: vgic-v3: " Marc Zyngier
2016-05-23 14:19   ` Christoffer Dall
2016-05-23 12:37 ` [PATCH 5/7] arm64: KVM: Make ICC_SRE_EL1 access return the configured SRE value Marc Zyngier
2016-05-24 12:45   ` Christoffer Dall
2016-05-23 12:37 ` [PATCH 6/7] arm64: KVM: vgic-v3: Prevent the guest from messing with ICC_SRE_EL1 Marc Zyngier
2016-05-24 12:49   ` Christoffer Dall
2016-05-23 12:37 ` [PATCH 7/7] arm64: KVM: vgic-v3: Relax synchronization when SRE==1 Marc Zyngier
2016-05-24 12:52   ` Christoffer Dall
2016-05-24 13:02     ` Marc Zyngier
2016-05-24 13:18       ` Christoffer Dall

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