From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E468C25B76 for ; Tue, 11 Jun 2024 10:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oYLKoHcaF5qJzcOyeFWF81sw0dMhK+lDUtBJyI0UqGI=; b=3AcRHub1HQCZqp Ml/MKUldRrmEB0UZ9sEdgJHHrVNqVZcEbJZU3WKwLULV+jHCDTSD7igxDhqgaQruysnub0v4jiUOk yESo8G28tTF0t83FcGDLZk7dTgaBR2t0ONv21MHIh9Zr5NHEmp8Uk6QykWLihKJXYxqwNH/ECBEz3 FV8IC+Rd3E5ZPlBt91aOEdWjtbbhcRmPT8RS/Hs0ow5dTT6XeGaSyobwBakRQ5zxoXI+LpIqWgQoi Tox13JGR6M7IiIEdqUVmO05Q+CL0yMobtoNJw4ANFvBfV7pjT/W0vB1BGvzI3BsOQqUdKIKwltN7t ne70IQFVf9fOK0tMC8YQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGyNx-00000008NRr-0gAj; Tue, 11 Jun 2024 10:05:49 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGyNr-00000008NNJ-2iKd for linux-arm-kernel@lists.infradead.org; Tue, 11 Jun 2024 10:05:47 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1718100343; x=1749636343; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IpeC1QAyGp7/ecmPqLy+8ePCuBDPCsaQb8tByibuhG4=; b=fUjY90FsOnBzIYrTL3u8jJCPBRQwvJfQ2Fv2pvv6lns8PPiku6RstsOq To0uhjbOl2mgVFM5FuBfLPmDi/pwlzelH9ttGYFCuzAquDv2SuOZ5/OjG b8htT0JEIKDytPNOsTrWrcs4f9actDSFNb3btxzBWzI/2fxp6kG3xEzx9 hRe0QXjyp3yPr5ft9aztJghHtMKP18OhlIhMgiTYDNa6nvbFBkGr7mjqD FItGf+X0iD7LhzpHYEKyllisqH0jOVoShWKklQgM9VvATIzOXhAP+viRO gCgkpU5Ea16wXAvxs+nSeVwIqaToPaDETELLA+LLsRzTY0eRAqPyxZCxV A==; X-CSE-ConnectionGUID: 1P99VBzoRRaTc8rrIT8Wsw== X-CSE-MsgGUID: vPHOmii7R1+khm3rIbi4Rg== X-IronPort-AV: E=Sophos;i="6.08,229,1712613600"; d="scan'208";a="37329397" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 11 Jun 2024 12:05:39 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 468ED163947; Tue, 11 Jun 2024 12:05:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1718100335; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=IpeC1QAyGp7/ecmPqLy+8ePCuBDPCsaQb8tByibuhG4=; b=B+lpaBY+5PQduUy26+YMD3o23CtOQFLQsz5x6J4Bt41aIzZw2yep1fBN9tF4XmrU3x84Mg AT+P7LWVDCPZxxfSli8hNWh3rI/T6pF0nxH4eRTMuuBfxQUR2sDYTFaZm+POUCx7MliTn/ Zk8kcDj0RolsedtKYfgHMw2sCKl7Qpm0xwZY6OMG8hx0HZU1sJE/U4cbPXcw21aKB8XDZk qz1GdbGMnMIZmC3+1B1p+wnnQ1DbexlkunLL8axoxwTmxPH15a/m1LQMkhDeQNITQVDGBr ThRuSVUFwwBuLkocjKXqSSzlo/T2uccWpUxv/PQmDfgsLQMiOJt6DwcYtG6evg== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dong Aisheng , linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Li , Frank Li Subject: Re: [PATCH v2 1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem Date: Tue, 11 Jun 2024 12:05:35 +0200 Message-ID: <5792284.DvuYhMxLoT@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20240610-imx8qm-dts-usb-v2-1-788417116fb1@nxp.com> References: <20240610-imx8qm-dts-usb-v2-0-788417116fb1@nxp.com> <20240610-imx8qm-dts-usb-v2-1-788417116fb1@nxp.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240611_030545_653045_A3CF562C X-CRM114-Status: GOOD ( 13.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Frank, Am Montag, 10. Juni 2024, 22:46:18 CEST schrieb Frank Li: > Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp. > = > Signed-off-by: Frank Li > --- > arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi | 63 +++++++++++++ > arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++= ++++++ > 2 files changed, 177 insertions(+) > = > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8-ss-lvds0.dtsi > new file mode 100644 > index 0000000000000..55fd60446ad21 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi > @@ -0,0 +1,63 @@ > +// SPDX-License-Identifier: GPL-2.0-only and MIT > + > +/* > + * Copyright 2024 NXP > + */ > + > +lvds0_subsys: bus@56240000 { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges =3D <0x56240000 0x0 0x56240000 0x10000>; > + > + qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56243000 0x4>; > + #clock-cells =3D <1>; > + clock-output-names =3D "mipi1_lis_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1>; > + }; > + > + qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5624300c 0x4>; > + #clock-cells =3D <1>; > + clock-output-names =3D "mipi1_pwm_lpcg_clk", > + "mipi1_pwm_lpcg_ipg_clk", > + "mipi1_pwm_lpcg_32k_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_PWM_0>; > + }; > + > + qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56243010 0x4>; > + #clock-cells =3D <1>; > + clock-output-names =3D "mipi1_i2c0_lpcg_clk", > + "mipi1_i2c0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>; > + }; > + > + qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 { > + compatible =3D "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; > + reg =3D <0x56244000 0x1000>; > + clock-names =3D "ipg", "per"; > + assigned-clocks =3D <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; Is IMX_SC_R_MIPI_1_I2C_0 actually correct? I would have assumed it's IMX_SC_R_MIPI_1_PWM_0. > + assigned-clock-rates =3D <24000000>; > + #pwm-cells =3D <3>; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_PWM_0>; > + status =3D "disabled"; > + }; > + > + qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 { > + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg =3D <0x56246000 0x1000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + interrupts =3D <8>; > + clock-names =3D "per", "ipg"; > + assigned-clocks =3D <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates =3D <24000000>; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>; > + status =3D "disabled"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8-ss-lvds1.dtsi > new file mode 100644 > index 0000000000000..12ae4f48e1e1c > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi This is only for imx8qm, no? It maybe makes sense to rename this file to imx8qm-ss-lvds1.dtsi Best regards, Alexander > @@ -0,0 +1,114 @@ > +// SPDX-License-Identifier: GPL-2.0-only and MIT > + > +/* > + * Copyright 2024 NXP > + */ > + > +lvds1_subsys: bus@57240000 { > + compatible =3D "simple-bus"; > + interrupt-parent =3D <&irqsteer_lvds1>; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges =3D <0x57240000 0x0 0x57240000 0x10000>; > + > + irqsteer_lvds1: interrupt-controller@57240000 { > + compatible =3D "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; > + reg =3D <0x57240000 0x1000>; > + interrupts =3D ; > + interrupt-controller; > + interrupt-parent =3D <&gic>; > + #interrupt-cells =3D <1>; > + clocks =3D <&lvds1_lis_lpcg IMX_LPCG_CLK_4>; > + clock-names =3D "ipg"; > + power-domains =3D <&pd IMX_SC_R_LVDS_1>; > + fsl,channel =3D <0>; > + fsl,num-irqs =3D <32>; > + }; > + > + lvds1_lis_lpcg: clock-controller@57243000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57243000 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&lvds_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "lvds1_lis_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_LVDS_1>; > + }; > + > + lvds1_pwm_lpcg: clock-controller@5724300c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5724300c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>, > + <&lvds_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "lvds1_pwm_lpcg_clk", > + "lvds1_pwm_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_LVDS_1_PWM_0>; > + }; > + > + lvds1_i2c0_lpcg: clock-controller@57243010 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57243010 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, > + <&lvds_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "lvds1_i2c0_lpcg_clk", > + "lvds1_i2c0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_LVDS_1_I2C_0>; > + }; > + > + lvds1_i2c1_lpcg: clock-controller@57243014 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57243014 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, > + <&lvds_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "lvds1_i2c1_lpcg_clk", > + "lvds1_i2c1_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_LVDS_1_I2C_0>; > + }; > + > + pwm_lvds1: pwm@57244000 { > + compatible =3D "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; > + reg =3D <0x57244000 0x1000>; > + clocks =3D <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>, > + <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>; > + clock-names =3D "ipg", "per"; > + assigned-clocks =3D <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates =3D <24000000>; > + #pwm-cells =3D <3>; > + power-domains =3D <&pd IMX_SC_R_LVDS_1_PWM_0>; > + status =3D "disabled"; > + }; > + > + i2c0_lvds1: i2c@57246000 { > + compatible =3D "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg =3D <0x57246000 0x1000>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + interrupts =3D <8>; > + clocks =3D <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>, > + <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>; > + clock-names =3D "per", "ipg"; > + assigned-clocks =3D <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates =3D <24000000>; > + power-domains =3D <&pd IMX_SC_R_LVDS_1_I2C_0>; > + status =3D "disabled"; > + }; > + > + i2c1_lvds1: i2c@57247000 { > + compatible =3D "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg =3D <0x57247000 0x1000>; > + interrupts =3D <9>; > + clocks =3D <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>, > + <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>; > + clock-names =3D "per", "ipg"; > + assigned-clocks =3D <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates =3D <24000000>; > + power-domains =3D <&pd IMX_SC_R_LVDS_1_I2C_0>; > + status =3D "disabled"; > + }; > +}; > = > = -- = TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel