[PATCH v2 0/8] ARM: V7M: Support caches

[PATCH v2 0/8] ARM: V7M: Support caches

[Vladimir Murzin]

Hi,

This patch set allows M-class cpus benefit of optional cache support.
It originally was written by Jonny, I've been keeping it locally mainly
rebasing over Linux versions.

The original idea behind patches was to reuse existing cache handling
code from v7A/R with help of extra macros to factor out cache handling
logic (v7M cache operations are provided via memory mapped interface
rather than co-processor instructions).
However, that idea was rejected and starting form this (v2) version
V7M cache logic lives into file and macros to indirect memory-mapped
operations stay there locally since they make it easier to follow the
code.

Along with the v7M cache support the first user (Cortex-M7) is
introduced.

Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
one showed significant boot speed-up.

Based on 4.8-rc2.

Thanks!
Vladimir

Changelog:

    v1 -> v2
        - dropped generalisation of read_cpuid() (per Russell)
	- M-class cache operations moved under it's own file and do not
	  interfere with A/R code (per Russell)

    RFC -> v1
        - use linux/io.h instead of asm/io.h (per Russell)
        - droped cast to void pointer in set_csselr; BASEADDR_V7M_SCB
          is already defined with a help of IOMEM macro (per Russell)
        - open-coded implantation of dccmvau and icimvau instead of
          macros, since the latter would mark the wring instruction as
          user-accessible (per Russell)
        - dccimvac is updated  per Russell preference
        - M_CLASS() macro is used instead of THUMB() where appropriate

Jonathan Austin (6):
  ARM: factor out CSSELR/CCSIDR operations that use cp15 directly
  ARM: V7M: Add addresses for mem-mapped V7M cache operations
  ARM: V7M: Add support for reading the CTR with read_cpuid_cachetype()
  ARM: V7M: Wire up caches for V7M processors with cache support.
  ARM: V7M: Indirect proc_info construction for V7M CPUs
  ARM: V7M: Add support for the Cortex-M7 processor

Vladimir Murzin (2):
  ARM: V7M: fix notrace variant of save_and_disable_irqs
  ARM: V7M: introduce cache operations

 arch/arm/include/asm/assembler.h  |    4 +
 arch/arm/include/asm/cachetype.h  |   39 ++++
 arch/arm/include/asm/cputype.h    |   15 +-
 arch/arm/include/asm/glue-cache.h |    4 -
 arch/arm/include/asm/v7m.h        |   22 ++
 arch/arm/kernel/head-nommu.S      |   16 +-
 arch/arm/kernel/setup.c           |   16 +-
 arch/arm/mm/Kconfig               |   10 +-
 arch/arm/mm/Makefile              |    2 +
 arch/arm/mm/cache-v7m.S           |  453 +++++++++++++++++++++++++++++++++++++
 arch/arm/mm/proc-macros.S         |   16 ++
 arch/arm/mm/proc-v7m.S            |  107 +++++++--
 12 files changed, 668 insertions(+), 36 deletions(-)
 create mode 100644 arch/arm/mm/cache-v7m.S

-- 
1.7.9.5

[PATCH v2 1/8] ARM: factor out CSSELR/CCSIDR operations that use cp15 directly

[Vladimir Murzin]

From: Jonathan Austin <jonathan.austin@arm.com>

Currently we use raw cp15 operations to access the cache setup data.

This patch abstracts the CSSELR and CCSIDR accessors out to a header so
that the implementation for them can be switched out as we do with other
cpu/cachetype operations.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/include/asm/cachetype.h |   24 ++++++++++++++++++++++++
 arch/arm/kernel/setup.c          |    7 ++-----
 2 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index 7ea7814..8609de8 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -56,4 +56,28 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
 	       (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
 }
 
+#define CSSELR_ICACHE	1
+#define CSSELR_DCACHE	0
+
+#define CSSELR_L1	(0 << 1)
+#define CSSELR_L2	(1 << 1)
+#define CSSELR_L3	(2 << 1)
+#define CSSELR_L4	(3 << 1)
+#define CSSELR_L5	(4 << 1)
+#define CSSELR_L6	(5 << 1)
+#define CSSELR_L7	(6 << 1)
+
+static inline void set_csselr(unsigned int cache_selector)
+{
+	asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
+}
+
+static inline unsigned int read_ccsidr(void)
+{
+	unsigned int val;
+
+	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
+	return val;
+}
+
 #endif
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index df7f2a7..2055490 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -290,12 +290,9 @@ static int cpu_has_aliasing_icache(unsigned int arch)
 	/* arch specifies the register format */
 	switch (arch) {
 	case CPU_ARCH_ARMv7:
-		asm("mcr	p15, 2, %0, c0, c0, 0 @ set CSSELR"
-		    : /* No output operands */
-		    : "r" (1));
+		set_csselr(CSSELR_ICACHE | CSSELR_L1);
 		isb();
-		asm("mrc	p15, 1, %0, c0, c0, 0 @ read CCSIDR"
-		    : "=r" (id_reg));
+		id_reg = read_ccsidr();
 		line_size = 4 << ((id_reg & 0x7) + 2);
 		num_sets = ((id_reg >> 13) & 0x7fff) + 1;
 		aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
-- 
1.7.9.5

[PATCH v2 2/8] ARM: V7M: Add addresses for mem-mapped V7M cache operations

[Vladimir Murzin]

From: Jonathan Austin <jonathan.austin@arm.com>

V7M implements cache operations similarly to V7A/R, however all operations
are performed via memory-mapped IO instead of co-processor operations.

This patch adds register definitions relevant to the V7M ARM architecture's
cache architecture.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/include/asm/v7m.h |   22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
index 615781c..1fd775c 100644
--- a/arch/arm/include/asm/v7m.h
+++ b/arch/arm/include/asm/v7m.h
@@ -24,6 +24,9 @@
 
 #define V7M_SCB_CCR			0x14
 #define V7M_SCB_CCR_STKALIGN			(1 << 9)
+#define V7M_SCB_CCR_DC				(1 << 16)
+#define V7M_SCB_CCR_IC				(1 << 17)
+#define V7M_SCB_CCR_BP				(1 << 18)
 
 #define V7M_SCB_SHPR2			0x1c
 #define V7M_SCB_SHPR3			0x20
@@ -47,6 +50,25 @@
 #define EXC_RET_STACK_MASK			0x00000004
 #define EXC_RET_THREADMODE_PROCESSSTACK		0xfffffffd
 
+/* Cache related definitions */
+
+#define	V7M_SCB_CLIDR		0x78	/* Cache Level ID register */
+#define	V7M_SCB_CTR		0x7c	/* Cache Type register */
+#define	V7M_SCB_CCSIDR		0x80	/* Cache size ID register */
+#define	V7M_SCB_CSSELR		0x84	/* Cache size selection register */
+
+/* Cache opeartions */
+#define	V7M_SCB_ICIALLU		0x250	/* I-cache invalidate all to PoU */
+#define	V7M_SCB_ICIMVAU		0x258	/* I-cache invalidate by MVA to PoU */
+#define	V7M_SCB_DCIMVAC		0x25c	/* D-cache invalidate by MVA to PoC */
+#define	V7M_SCB_DCISW		0x260	/* D-cache invalidate by set-way */
+#define	V7M_SCB_DCCMVAU		0x264	/* D-cache clean by MVA to PoU */
+#define	V7M_SCB_DCCMVAC		0x268	/* D-cache clean by MVA to PoC */
+#define	V7M_SCB_DCCSW		0x26c	/* D-cache clean by set-way */
+#define	V7M_SCB_DCCIMVAC	0x270	/* D-cache clean and invalidate by MVA to PoC */
+#define	V7M_SCB_DCCISW		0x274	/* D-cache clean and invalidate by set-way */
+#define	V7M_SCB_BPIALL		0x278	/* D-cache clean and invalidate by set-way */
+
 #ifndef __ASSEMBLY__
 
 enum reboot_mode;
-- 
1.7.9.5

[PATCH v2 3/8] ARM: V7M: Add support for reading the CTR with read_cpuid_cachetype()

[Vladimir Murzin]

From: Jonathan Austin <jonathan.austin@arm.com>

With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/include/asm/cachetype.h |   15 +++++++++++++++
 arch/arm/include/asm/cputype.h   |   15 ++++++++++-----
 arch/arm/kernel/setup.c          |    9 +++++----
 3 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index 8609de8..01509ae 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -67,6 +67,7 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
 #define CSSELR_L6	(5 << 1)
 #define CSSELR_L7	(6 << 1)
 
+#ifndef CONFIG_CPU_V7M
 static inline void set_csselr(unsigned int cache_selector)
 {
 	asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
@@ -79,5 +80,19 @@ static inline unsigned int read_ccsidr(void)
 	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
 	return val;
 }
+#else /* CONFIG_CPU_V7M */
+#include <linux/io.h>
+#include "asm/v7m.h"
+
+static inline void set_csselr(unsigned int cache_selector)
+{
+	writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
+}
+
+static inline unsigned int read_ccsidr(void)
+{
+	return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
+}
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 1ee94c7..bd753ff 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -152,6 +152,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
 	return read_cpuid(CPUID_ID);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+	return read_cpuid(CPUID_CACHETYPE);
+}
+
 #elif defined(CONFIG_CPU_V7M)
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
@@ -159,6 +164,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
 	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+	return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
+}
+
 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
@@ -193,11 +203,6 @@ static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 }
 
-static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
-{
-	return read_cpuid(CPUID_CACHETYPE);
-}
-
 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 {
 	return read_cpuid(CPUID_TCM);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 2055490..f35f9eb 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -312,11 +312,12 @@ static void __init cacheid_init(void)
 {
 	unsigned int arch = cpu_architecture();
 
-	if (arch == CPU_ARCH_ARMv7M) {
-		cacheid = 0;
-	} else if (arch >= CPU_ARCH_ARMv6) {
+	if (arch >= CPU_ARCH_ARMv6) {
 		unsigned int cachetype = read_cpuid_cachetype();
-		if ((cachetype & (7 << 29)) == 4 << 29) {
+
+		if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {
+			cacheid = 0;
+		} else if ((cachetype & (7 << 29)) == 4 << 29) {
 			/* ARMv7 register format */
 			arch = CPU_ARCH_ARMv7;
 			cacheid = CACHEID_VIPT_NONALIASING;
-- 
1.7.9.5

[PATCH v2 4/8] ARM: V7M: fix notrace variant of save_and_disable_irqs

[Vladimir Murzin]

Commit 8e43a905 "ARM: 7325/1: fix v7 boot with lockdep enabled"
introduced notrace variant of save_and_disable_irqs to balance notrace
variant of restore_irqs; however V7M case has been missed. It was not
noticed because cache-v7.S the only place where notrace variant is used.
So fix it, since we are going to extend V7 cache routines to handle V7M
case too.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/include/asm/assembler.h |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 4eaea21..68b06f9 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -159,7 +159,11 @@
 	.endm
 
 	.macro	save_and_disable_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	mrs	\oldcpsr, primask
+#else
 	mrs	\oldcpsr, cpsr
+#endif
 	disable_irq_notrace
 	.endm
 
-- 
1.7.9.5

[PATCH v2 5/8] ARM: V7M: introduce cache operations

[Vladimir Murzin]

This commit implements the cache operation for V7M.

It is based on V7 counterpart and differs as follows:
- cache operations are memory mapped
- only Thumb instruction set is supported
- we don't handle user access faults

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/mm/cache-v7m.S   |  453 +++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mm/proc-macros.S |   16 ++
 2 files changed, 469 insertions(+)
 create mode 100644 arch/arm/mm/cache-v7m.S

diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S
new file mode 100644
index 0000000..816a7e4
--- /dev/null
+++ b/arch/arm/mm/cache-v7m.S
@@ -0,0 +1,453 @@
+/*
+ *  linux/arch/arm/mm/cache-v7m.S
+ *
+ *  Based on linux/arch/arm/mm/cache-v7.S
+ *
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7M processor support.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+#include <asm/unwind.h>
+#include <asm/v7m.h>
+
+#include "proc-macros.S"
+
+/* Generic V7M read/write macros for memory mapped cache operations */
+.macro v7m_cache_read, rt, reg
+	movw	\rt, #:lower16:BASEADDR_V7M_SCB + \reg
+	movt	\rt, #:upper16:BASEADDR_V7M_SCB + \reg
+	ldr     \rt, [\rt]
+.endm
+
+.macro v7m_cacheop, rt, tmp, op, c = al
+	movw\c	\tmp, #:lower16:BASEADDR_V7M_SCB + \op
+	movt\c	\tmp, #:upper16:BASEADDR_V7M_SCB + \op
+	str\c	\rt, [\tmp]
+.endm
+
+
+.macro	read_ccsidr, rt
+	v7m_cache_read \rt, V7M_SCB_CCSIDR
+.endm
+
+.macro read_clidr, rt
+	v7m_cache_read \rt, V7M_SCB_CLIDR
+.endm
+
+.macro	write_csselr, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
+.endm
+
+/*
+ * dcisw: Invalidate data cache by set/way
+ */
+.macro dcisw, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
+.endm
+
+/*
+ * dccisw: Clean and invalidate data cache by set/way
+ */
+.macro dccisw, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
+.endm
+
+/*
+ * dccimvac: Clean and invalidate data cache line by MVA to PoC.
+ */
+.irp    c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
+.macro dccimvac\c, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
+.endm
+.endr
+
+/*
+ * dcimvac: Invalidate data cache line by MVA to PoC
+ */
+.macro dcimvac, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC
+.endm
+
+/*
+ * dccmvau: Clean data cache line by MVA to PoU
+ */
+.macro dccmvau, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
+.endm
+
+/*
+ * dccmvac: Clean data cache line by MVA to PoC
+ */
+.macro dccmvac,  rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
+.endm
+
+/*
+ * icimvau: Invalidate instruction caches by MVA to PoU
+ */
+.macro icimvau, rt, tmp
+	v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
+.endm
+
+/*
+ * Invalidate the icache, inner shareable if SMP, invalidate BTB for UP.
+ * rt data ignored by ICIALLU(IS), so can be used for the address
+ */
+.macro invalidate_icache, rt
+	v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
+	mov \rt, #0
+.endm
+
+/*
+ * Invalidate the BTB, inner shareable if SMP.
+ * rt data ignored by BPIALL, so it can be used for the address
+ */
+.macro invalidate_bp, rt
+	v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
+	mov \rt, #0
+.endm
+
+ENTRY(v7m_invalidate_l1)
+	mov	r0, #0
+
+	write_csselr r0, r1
+	read_ccsidr r0
+
+	movw	r1, #0x7fff
+	and	r2, r1, r0, lsr #13
+
+	movw	r1, #0x3ff
+
+	and	r3, r1, r0, lsr #3      @ NumWays - 1
+	add	r2, r2, #1              @ NumSets
+
+	and	r0, r0, #0x7
+	add	r0, r0, #4      @ SetShift
+
+	clz	r1, r3          @ WayShift
+	add	r4, r3, #1      @ NumWays
+1:	sub	r2, r2, #1      @ NumSets--
+	mov	r3, r4          @ Temp = NumWays
+2:	subs	r3, r3, #1      @ Temp--
+	mov	r5, r3, lsl r1
+	mov	r6, r2, lsl r0
+	orr	r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+	dcisw	r5, r6
+	bgt	2b
+	cmp	r2, #0
+	bgt	1b
+	dsb	st
+	isb
+	ret	lr
+ENDPROC(v7m_invalidate_l1)
+
+/*
+ *	v7m_flush_icache_all()
+ *
+ *	Flush the whole I-cache.
+ *
+ *	Registers:
+ *	r0 - set to 0
+ */
+ENTRY(v7m_flush_icache_all)
+	invalidate_icache r0
+	ret	lr
+ENDPROC(v7m_flush_icache_all)
+
+/*
+ *	v7m_flush_dcache_all()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: r0-r7, r9-r11
+ */
+ENTRY(v7m_flush_dcache_all)
+	dmb					@ ensure ordering with previous memory accesses
+	read_clidr r0
+	mov	r3, r0, lsr #23			@ move LoC into position
+	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
+	beq	finished			@ if loc is 0, then no need to clean
+start_flush_levels:
+	mov	r10, #0				@ start clean at cache level 0
+flush_levels:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+	and	r1, r1, #7			@ mask of the bits for current cache only
+	cmp	r1, #2				@ see what cache we have at this level
+	blt	skip				@ skip if no cache, or just i-cache
+#ifdef CONFIG_PREEMPT
+	save_and_disable_irqs_notrace r9	@ make cssr&csidr read atomic
+#endif
+	write_csselr r10, r1			@ set current cache level
+	isb					@ isb to sych the new cssr&csidr
+	read_ccsidr r1				@ read the new csidr
+#ifdef CONFIG_PREEMPT
+	restore_irqs_notrace r9
+#endif
+	and	r2, r1, #7			@ extract the length of the cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	movw	r4, #0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+	clz	r5, r4				@ find bit position of way size increment
+	movw	r7, #0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+loop1:
+	mov	r9, r7				@ create working copy of max index
+loop2:
+	lsl	r6, r4, r5
+	orr	r11, r10, r6			@ factor way and cache number into r11
+	lsl	r6, r9, r2
+	orr	r11, r11, r6			@ factor index number into r11
+	dccisw	r11, r6				@ clean/invalidate by set/way
+	subs	r9, r9, #1			@ decrement the index
+	bge	loop2
+	subs	r4, r4, #1			@ decrement the way
+	bge	loop1
+skip:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	flush_levels
+finished:
+	mov	r10, #0				@ swith back to cache level 0
+	write_csselr r10, r3			@ select current cache level in cssr
+	dsb	st
+	isb
+	ret	lr
+ENDPROC(v7m_flush_dcache_all)
+
+/*
+ *	v7m_flush_cache_all()
+ *
+ *	Flush the entire cache system.
+ *  The data cache flush is now achieved using atomic clean / invalidates
+ *  working outwards from L1 cache. This is done using Set/Way based cache
+ *  maintenance instructions.
+ *  The instruction cache can still be invalidated back to the point of
+ *  unification in a single instruction.
+ *
+ */
+ENTRY(v7m_flush_kern_cache_all)
+	stmfd	sp!, {r4-r7, r9-r11, lr}
+	bl	v7m_flush_dcache_all
+	invalidate_icache r0
+	ldmfd	sp!, {r4-r7, r9-r11, lr}
+	ret	lr
+ENDPROC(v7m_flush_kern_cache_all)
+
+/*
+ *	v7m_flush_cache_all()
+ *
+ *	Flush all TLB entries in a particular address space
+ *
+ *	- mm    - mm_struct describing address space
+ */
+ENTRY(v7m_flush_user_cache_all)
+	/*FALLTHROUGH*/
+
+/*
+ *	v7m_flush_cache_range(start, end, flags)
+ *
+ *	Flush a range of TLB entries in the specified address space.
+ *
+ *	- start - start address (may not be aligned)
+ *	- end   - end address (exclusive, may not be aligned)
+ *	- flags	- vm_area_struct flags describing address space
+ *
+ *	It is assumed that:
+ *	- we have a VIPT cache.
+ */
+ENTRY(v7m_flush_user_cache_range)
+	ret	lr
+ENDPROC(v7m_flush_user_cache_all)
+ENDPROC(v7m_flush_user_cache_range)
+
+/*
+ *	v7m_coherent_kern_range(start,end)
+ *
+ *	Ensure that the I and D caches are coherent within specified
+ *	region.  This is typically used when code has been written to
+ *	a memory region, and will be executed.
+ *
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ *
+ *	It is assumed that:
+ *	- the Icache does not read data from the write buffer
+ */
+ENTRY(v7m_coherent_kern_range)
+	/* FALLTHROUGH */
+
+/*
+ *	v7m_coherent_user_range(start,end)
+ *
+ *	Ensure that the I and D caches are coherent within specified
+ *	region.  This is typically used when code has been written to
+ *	a memory region, and will be executed.
+ *
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ *
+ *	It is assumed that:
+ *	- the Icache does not read data from the write buffer
+ */
+ENTRY(v7m_coherent_user_range)
+ UNWIND(.fnstart		)
+	dcache_line_size r2, r3
+	sub	r3, r2, #1
+	bic	r12, r0, r3
+1:
+/*
+ * We use open coded version of dccmvau otherwise USER() would
+ * point@movw instruction.
+ */
+	dccmvau	r12, r3
+	add	r12, r12, r2
+	cmp	r12, r1
+	blo	1b
+	dsb	ishst
+	icache_line_size r2, r3
+	sub	r3, r2, #1
+	bic	r12, r0, r3
+2:
+	icimvau r12, r3
+	add	r12, r12, r2
+	cmp	r12, r1
+	blo	2b
+	invalidate_bp r0
+	dsb	ishst
+	isb
+	ret	lr
+ UNWIND(.fnend		)
+ENDPROC(v7m_coherent_kern_range)
+ENDPROC(v7m_coherent_user_range)
+
+/*
+ *	v7m_flush_kern_dcache_area(void *addr, size_t size)
+ *
+ *	Ensure that the data held in the page kaddr is written back
+ *	to the page in question.
+ *
+ *	- addr	- kernel address
+ *	- size	- region size
+ */
+ENTRY(v7m_flush_kern_dcache_area)
+	dcache_line_size r2, r3
+	add	r1, r0, r1
+	sub	r3, r2, #1
+	bic	r0, r0, r3
+1:
+	dccimvac r0, r3		@ clean & invalidate D line / unified line
+	add	r0, r0, r2
+	cmp	r0, r1
+	blo	1b
+	dsb	st
+	ret	lr
+ENDPROC(v7m_flush_kern_dcache_area)
+
+/*
+ *	v7m_dma_inv_range(start,end)
+ *
+ *	Invalidate the data cache within the specified region; we will
+ *	be performing a DMA operation in this region and we want to
+ *	purge old data in the cache.
+ *
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+v7m_dma_inv_range:
+	dcache_line_size r2, r3
+	sub	r3, r2, #1
+	tst	r0, r3
+	bic	r0, r0, r3
+	dccimvacne r0, r3
+	subne	r3, r2, #1	@ restore r3, corrupted by v7m's dccimvac
+	tst	r1, r3
+	bic	r1, r1, r3
+	dccimvacne r1, r3
+1:
+	dcimvac r0, r3
+	add	r0, r0, r2
+	cmp	r0, r1
+	blo	1b
+	dsb	st
+	ret	lr
+ENDPROC(v7m_dma_inv_range)
+
+/*
+ *	v7m_dma_clean_range(start,end)
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+v7m_dma_clean_range:
+	dcache_line_size r2, r3
+	sub	r3, r2, #1
+	bic	r0, r0, r3
+1:
+	dccmvac r0, r3			@ clean D / U line
+	add	r0, r0, r2
+	cmp	r0, r1
+	blo	1b
+	dsb	st
+	ret	lr
+ENDPROC(v7m_dma_clean_range)
+
+/*
+ *	v7m_dma_flush_range(start,end)
+ *	- start   - virtual start address of region
+ *	- end     - virtual end address of region
+ */
+ENTRY(v7m_dma_flush_range)
+	dcache_line_size r2, r3
+	sub	r3, r2, #1
+	bic	r0, r0, r3
+1:
+	dccimvac r0, r3			 @ clean & invalidate D / U line
+	add	r0, r0, r2
+	cmp	r0, r1
+	blo	1b
+	dsb	st
+	ret	lr
+ENDPROC(v7m_dma_flush_range)
+
+/*
+ *	dma_map_area(start, size, dir)
+ *	- start	- kernel virtual start address
+ *	- size	- size of region
+ *	- dir	- DMA direction
+ */
+ENTRY(v7m_dma_map_area)
+	add	r1, r1, r0
+	teq	r2, #DMA_FROM_DEVICE
+	beq	v7m_dma_inv_range
+	b	v7m_dma_clean_range
+ENDPROC(v7m_dma_map_area)
+
+/*
+ *	dma_unmap_area(start, size, dir)
+ *	- start	- kernel virtual start address
+ *	- size	- size of region
+ *	- dir	- DMA direction
+ */
+ENTRY(v7m_dma_unmap_area)
+	add	r1, r1, r0
+	teq	r2, #DMA_TO_DEVICE
+	bne	v7m_dma_inv_range
+	ret	lr
+ENDPROC(v7m_dma_unmap_area)
+
+	.globl	v7m_flush_kern_cache_louis
+	.equ	v7m_flush_kern_cache_louis, v7m_flush_kern_cache_all
+
+	__INITDATA
+
+	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+	define_cache_functions v7m
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index c671f34..0d40c28 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -7,6 +7,10 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 
+#ifdef CONFIG_CPU_V7M
+#include <asm/v7m.h>
+#endif
+
 /*
  * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
  */
@@ -70,7 +74,13 @@
  * on ARMv7.
  */
 	.macro	dcache_line_size, reg, tmp
+#ifdef CONFIG_CPU_V7M
+	movw	\tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
+	movt	\tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
+	ldr     \tmp, [\tmp]
+#else
 	mrc	p15, 0, \tmp, c0, c0, 1		@ read ctr
+#endif
 	lsr	\tmp, \tmp, #16
 	and	\tmp, \tmp, #0xf		@ cache line size encoding
 	mov	\reg, #4			@ bytes per word
@@ -82,7 +92,13 @@
  * on ARMv7.
  */
 	.macro	icache_line_size, reg, tmp
+#ifdef CONFIG_CPU_V7M
+	movw	\tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
+	movt	\tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
+	ldr     \tmp, [\tmp]
+#else
 	mrc	p15, 0, \tmp, c0, c0, 1		@ read ctr
+#endif
 	and	\tmp, \tmp, #0xf		@ cache line size encoding
 	mov	\reg, #4			@ bytes per word
 	mov	\reg, \reg, lsl \tmp		@ actual cache line size
-- 
1.7.9.5

[PATCH v2 6/8] ARM: V7M: Wire up caches for V7M processors with cache support.

[Vladimir Murzin]

From: Jonathan Austin <jonathan.austin@arm.com>

This patch does the plumbing required to invoke the V7M cache code added
in earlier patches in this series, although there is no users for that
yet.

In order to honour the I/D cache disable config options, this patch changes
the mechanism by which the CCR is set on boot, to be more like V7A/R.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/include/asm/glue-cache.h |    4 ----
 arch/arm/kernel/head-nommu.S      |   16 +++++++++++++++-
 arch/arm/mm/Kconfig               |   10 +++++++---
 arch/arm/mm/Makefile              |    2 ++
 arch/arm/mm/proc-v7m.S            |    5 ++---
 5 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index cab07f6..01c3d92 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -118,11 +118,7 @@
 #endif
 
 #if defined(CONFIG_CPU_V7M)
-# ifdef _CACHE
 #  define MULTI_CACHE 1
-# else
-#  define _CACHE nop
-# endif
 #endif
 
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index fb1a69e..6b4eb27 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -158,7 +158,21 @@ __after_proc_init:
 	bic	r0, r0, #CR_V
 #endif
 	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
-#endif /* CONFIG_CPU_CP15 */
+#elif defined (CONFIG_CPU_V7M)
+	/* For V7M systems we want to modify the CCR similarly to the SCTLR */
+#ifdef CONFIG_CPU_DCACHE_DISABLE
+	bic	r0, r0, #V7M_SCB_CCR_DC
+#endif
+#ifdef CONFIG_CPU_BPREDICT_DISABLE
+	bic	r0, r0, #V7M_SCB_CCR_BP
+#endif
+#ifdef CONFIG_CPU_ICACHE_DISABLE
+	bic	r0, r0, #V7M_SCB_CCR_IC
+#endif
+	movw	r3, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
+	movt	r3, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
+	str	r0, [r3]
+#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
 	ret	lr
 ENDPROC(__after_proc_init)
 	.ltorg
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d15a7fe..e613122 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -403,6 +403,7 @@ config CPU_V7M
 	bool
 	select CPU_32v7M
 	select CPU_ABRT_NOMMU
+	select CPU_CACHE_V7M
 	select CPU_CACHE_NOP
 	select CPU_PABRT_LEGACY
 	select CPU_THUMBONLY
@@ -518,6 +519,9 @@ config CPU_CACHE_VIPT
 config CPU_CACHE_FA
 	bool
 
+config CPU_CACHE_V7M
+	bool
+
 if MMU
 # The copy-page model
 config CPU_COPY_V4WT
@@ -750,14 +754,14 @@ config CPU_HIGH_VECTOR
 
 config CPU_ICACHE_DISABLE
 	bool "Disable I-Cache (I-bit)"
-	depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
+	depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
 	help
 	  Say Y here to disable the processor instruction cache. Unless
 	  you have a reason not to or are unsure, say N.
 
 config CPU_DCACHE_DISABLE
 	bool "Disable D-Cache (C-bit)"
-	depends on CPU_CP15 && !SMP
+	depends on (CPU_CP15 && !SMP) || CPU_V7M
 	help
 	  Say Y here to disable the processor data cache. Unless
 	  you have a reason not to or are unsure, say N.
@@ -792,7 +796,7 @@ config CPU_CACHE_ROUND_ROBIN
 
 config CPU_BPREDICT_DISABLE
 	bool "Disable branch prediction"
-	depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
+	depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
 	help
 	  Say Y here to disable branch prediction.  If unsure, say N.
 
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 7f76d96..e75abae 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -43,9 +43,11 @@ obj-$(CONFIG_CPU_CACHE_V6)	+= cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)	+= cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)	+= cache-fa.o
 obj-$(CONFIG_CPU_CACHE_NOP)	+= cache-nop.o
+obj-$(CONFIG_CPU_CACHE_V7M)	+= cache-v7m.o
 
 AFLAGS_cache-v6.o	:=-Wa,-march=armv6
 AFLAGS_cache-v7.o	:=-Wa,-march=armv7-a
+AFLAGS_cache-v7m.o	:=-Wa,-march=armv7-m
 
 obj-$(CONFIG_CPU_COPY_V4WT)	+= copypage-v4wt.o
 obj-$(CONFIG_CPU_COPY_V4WB)	+= copypage-v4wb.o
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 7229d8d..11f5816 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -118,9 +118,8 @@ __v7m_setup:
 
 	@ Configure the System Control Register to ensure 8-byte stack alignment
 	@ Note the STKALIGN bit is either RW or RAO.
-	ldr	r12, [r0, V7M_SCB_CCR]	@ system control register
-	orr	r12, #V7M_SCB_CCR_STKALIGN
-	str	r12, [r0, V7M_SCB_CCR]
+	ldr	r0, [r0, V7M_SCB_CCR]   @ system control register
+	orr	r0, #V7M_SCB_CCR_STKALIGN
 	ret	lr
 ENDPROC(__v7m_setup)
 
-- 
1.7.9.5

[PATCH v2 7/8] ARM: V7M: Indirect proc_info construction for V7M CPUs

[Vladimir Murzin]

From: Jonathan Austin <jonathan.austin@arm.com>

This patch copies the method used for V7A/R CPUs to specify differing
processor info for different cores.

This patch differentiates Cortex-M3 and Cortex-M4 and leaves a fallback case
for any other V7M processors.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/mm/proc-v7m.S |   46 +++++++++++++++++++++++++++++++++++-----------
 1 file changed, 35 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 11f5816..796a983 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -132,6 +132,40 @@ ENDPROC(__v7m_setup)
 
 	.section ".proc.info.init", #alloc
 
+.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
+	.long	0			/* proc_info_list.__cpu_mm_mmu_flags */
+	.long	0			/* proc_info_list.__cpu_io_mmu_flags */
+	initfn	\initfunc, \name
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \hwcaps
+	.long	cpu_v7m_name
+	.long   \proc_fns
+	.long	0			/* proc_info_list.tlb */
+	.long	0			/* proc_info_list.user */
+	.long	\cache_fns
+.endm
+
+	/*
+	 * Match ARM Cortex-M4 processor.
+	 */
+	.type	__v7m_cm4_proc_info, #object
+__v7m_cm4_proc_info:
+	.long	0x410fc240		/* ARM Cortex-M4 0xC24 */
+	.long	0xff0ffff0		/* Mask off revision, patch release */
+	__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
+	.size	__v7m_cm4_proc_info, . - __v7m_cm4_proc_info
+
+	/*
+	 * Match ARM Cortex-M3 processor.
+	 */
+	.type	__v7m_cm3_proc_info, #object
+__v7m_cm3_proc_info:
+	.long	0x410fc230		/* ARM Cortex-M3 0xC23 */
+	.long	0xff0ffff0		/* Mask off revision, patch release */
+	__v7m_proc __v7m_cm3_proc_info, __v7m_setup
+	.size	__v7m_cm3_proc_info, . - __v7m_cm3_proc_info
+
 	/*
 	 * Match any ARMv7-M processor core.
 	 */
@@ -139,16 +173,6 @@ ENDPROC(__v7m_setup)
 __v7m_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   0			@ proc_info_list.__cpu_mm_mmu_flags
-	.long   0			@ proc_info_list.__cpu_io_mmu_flags
-	initfn	__v7m_setup, __v7m_proc_info	@ proc_info_list.__cpu_flush
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
-	.long	cpu_v7m_name
-	.long	v7m_processor_functions	@ proc_info_list.proc
-	.long	0			@ proc_info_list.tlb
-	.long	0			@ proc_info_list.user
-	.long	nop_cache_fns		@ proc_info_list.cache
+	__v7m_proc __v7m_proc_info, __v7m_setup
 	.size	__v7m_proc_info, . - __v7m_proc_info
 
-- 
1.7.9.5

[PATCH v2 8/8] ARM: V7M: Add support for the Cortex-M7 processor

[Vladimir Murzin]

From: Jonathan Austin <jonathan.austin@arm.com>

Cortex-M7 is a new member of the V7M processor family that adds, among
other things, caches over the features available in Cortex-M4.

This patch adds support for recognising the processor at boot time, and
make use of recently introduced cache functions.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm/mm/proc-v7m.S |   56 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 796a983..e6786f0 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -74,14 +74,42 @@ ENTRY(cpu_v7m_do_resume)
 ENDPROC(cpu_v7m_do_resume)
 #endif
 
+ENTRY(cpu_cm7_dcache_clean_area)
+	dcache_line_size r2, r3
+	movw	r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
+	movt	r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
+
+1:	str	r0, [r3]		@ clean D entry
+	add	r0, r0, r2
+	subs	r1, r1, r2
+	bhi	1b
+	dsb
+	ret	lr
+ENDPROC(cpu_cm7_dcache_clean_area)
+
+ENTRY(cpu_cm7_proc_fin)
+	movw	r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
+	movt	r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
+	ldr	r0, [r2]
+	bic	r0, r0, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC)
+	str	r0, [r2]
+	ret	lr
+ENDPROC(cpu_cm7_proc_fin)
+
 	.section ".text.init", #alloc, #execinstr
 
+__v7m_cm7_setup:
+	mov	r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
+	b	__v7m_setup_cont
 /*
  *	__v7m_setup
  *
  *	This should be able to cover all ARMv7-M cores.
  */
 __v7m_setup:
+	mov	r8, 0
+
+__v7m_setup_cont:
 	@ Configure the vector table base address
 	ldr	r0, =BASEADDR_V7M_SCB
 	ldr	r12, =vector_table
@@ -116,14 +144,32 @@ __v7m_setup:
 	mov	r1, #1
 	msr	control, r1		@ Thread mode has unpriviledged access
 
+	@ Configure caches (if implemented)
+	teq     r8, #0
+	stmneia	r12, {r0-r6, lr}	@ v7m_invalidate_l1 touches r0-r6
+	blne	v7m_invalidate_l1
+	teq     r8, #0			@ re-evalutae condition
+	ldmneia	r12, {r0-r6, lr}
+
 	@ Configure the System Control Register to ensure 8-byte stack alignment
 	@ Note the STKALIGN bit is either RW or RAO.
 	ldr	r0, [r0, V7M_SCB_CCR]   @ system control register
 	orr	r0, #V7M_SCB_CCR_STKALIGN
+	orr	r0, r0, r8
+
 	ret	lr
 ENDPROC(__v7m_setup)
 
+/*
+ * Cortex-M7 processor functions
+ */
+	globl_equ	cpu_cm7_proc_init,	cpu_v7m_proc_init
+	globl_equ	cpu_cm7_reset,		cpu_v7m_reset
+	globl_equ	cpu_cm7_do_idle,	cpu_v7m_do_idle
+	globl_equ	cpu_cm7_switch_mm,	cpu_v7m_switch_mm
+
 	define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
+	define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
 
 	.section ".rodata"
 	string cpu_arch_name, "armv7m"
@@ -147,6 +193,16 @@ ENDPROC(__v7m_setup)
 .endm
 
 	/*
+	 * Match ARM Cortex-M7 processor.
+	 */
+	.type	__v7m_cm7_proc_info, #object
+__v7m_cm7_proc_info:
+	.long	0x410fc270		/* ARM Cortex-M7 0xC27 */
+	.long	0xff0ffff0		/* Mask off revision, patch release */
+	__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
+	.size	__v7m_cm7_proc_info, . - __v7m_cm7_proc_info
+
+	/*
 	 * Match ARM Cortex-M4 processor.
 	 */
 	.type	__v7m_cm4_proc_info, #object
-- 
1.7.9.5

[PATCH v2 0/8] ARM: V7M: Support caches

[Russell King - ARM Linux]

On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
> This patch set allows M-class cpus benefit of optional cache support.
> It originally was written by Jonny, I've been keeping it locally mainly
> rebasing over Linux versions.
> 
> The original idea behind patches was to reuse existing cache handling
> code from v7A/R with help of extra macros to factor out cache handling
> logic (v7M cache operations are provided via memory mapped interface
> rather than co-processor instructions).
> However, that idea was rejected and starting form this (v2) version
> V7M cache logic lives into file and macros to indirect memory-mapped
> operations stay there locally since they make it easier to follow the
> code.
> 
> Along with the v7M cache support the first user (Cortex-M7) is
> introduced.
> 
> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
> one showed significant boot speed-up.

>From a quick read through, the approach looks sane, and I think I'm
now happy with these.

Thanks.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

[PATCH v2 0/8] ARM: V7M: Support caches

[Vladimir Murzin]

On 18/08/16 15:53, Russell King - ARM Linux wrote:
> On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
>> This patch set allows M-class cpus benefit of optional cache support.
>> It originally was written by Jonny, I've been keeping it locally mainly
>> rebasing over Linux versions.
>>
>> The original idea behind patches was to reuse existing cache handling
>> code from v7A/R with help of extra macros to factor out cache handling
>> logic (v7M cache operations are provided via memory mapped interface
>> rather than co-processor instructions).
>> However, that idea was rejected and starting form this (v2) version
>> V7M cache logic lives into file and macros to indirect memory-mapped
>> operations stay there locally since they make it easier to follow the
>> code.
>>
>> Along with the v7M cache support the first user (Cortex-M7) is
>> introduced.
>>
>> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
>> one showed significant boot speed-up.
> 
>>From a quick read through, the approach looks sane, and I think I'm
> now happy with these.
> 

Thanks!

Is it acceptable if patches hang on a list for awhile, so people (I'm
looking at Alex and  Szemz?) can test them?

Vladimir

> Thanks.
> 

[PATCH v2 0/8] ARM: V7M: Support caches

[Russell King - ARM Linux]

On Thu, Aug 18, 2016 at 03:57:34PM +0100, Vladimir Murzin wrote:
> On 18/08/16 15:53, Russell King - ARM Linux wrote:
> > On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
> >> This patch set allows M-class cpus benefit of optional cache support.
> >> It originally was written by Jonny, I've been keeping it locally mainly
> >> rebasing over Linux versions.
> >>
> >> The original idea behind patches was to reuse existing cache handling
> >> code from v7A/R with help of extra macros to factor out cache handling
> >> logic (v7M cache operations are provided via memory mapped interface
> >> rather than co-processor instructions).
> >> However, that idea was rejected and starting form this (v2) version
> >> V7M cache logic lives into file and macros to indirect memory-mapped
> >> operations stay there locally since they make it easier to follow the
> >> code.
> >>
> >> Along with the v7M cache support the first user (Cortex-M7) is
> >> introduced.
> >>
> >> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
> >> one showed significant boot speed-up.
> > 
> >>From a quick read through, the approach looks sane, and I think I'm
> > now happy with these.
> > 
> 
> Thanks!
> 
> Is it acceptable if patches hang on a list for awhile, so people (I'm
> looking at Alex and  Szemz?) can test them?

Of course.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

[PATCH v2 0/8] ARM: V7M: Support caches

[Vladimir Murzin]

On 18/08/16 16:11, Russell King - ARM Linux wrote:
> On Thu, Aug 18, 2016 at 03:57:34PM +0100, Vladimir Murzin wrote:
>> On 18/08/16 15:53, Russell King - ARM Linux wrote:
>>> On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
>>>> This patch set allows M-class cpus benefit of optional cache support.
>>>> It originally was written by Jonny, I've been keeping it locally mainly
>>>> rebasing over Linux versions.
>>>>
>>>> The original idea behind patches was to reuse existing cache handling
>>>> code from v7A/R with help of extra macros to factor out cache handling
>>>> logic (v7M cache operations are provided via memory mapped interface
>>>> rather than co-processor instructions).
>>>> However, that idea was rejected and starting form this (v2) version
>>>> V7M cache logic lives into file and macros to indirect memory-mapped
>>>> operations stay there locally since they make it easier to follow the
>>>> code.
>>>>
>>>> Along with the v7M cache support the first user (Cortex-M7) is
>>>> introduced.
>>>>
>>>> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
>>>> one showed significant boot speed-up.
>>>
>>> >From a quick read through, the approach looks sane, and I think I'm
>>> now happy with these.
>>>
>>
>> Thanks!
>>
>> Is it acceptable if patches hang on a list for awhile, so people (I'm
>> looking at Alex and  Szemz?) can test them?
> 
> Of course.
> 

Russell, given that it was tested on platforms with and without cache
support, I've just dropped this set into patch system. Please, let me
know if you see issues with that.

Thanks
Vladimir

[PATCH v2 0/8] ARM: V7M: Support caches

[Szemző András]

Hi,

> On 18 Aug 2016, at 16:57, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
> 
> Is it acceptable if patches hang on a list for awhile, so people (I'm
> looking at Alex and  Szemz?) can test them?
> 

This is my first email to the list, so sorry If I make mistakes with my report,
I still need to learn?

I have tested these patches on my custom board with ATMEL SAME70 armv7m SoC.

With default memory mapping configured MPU booting and rebooting works fine, I don?t see any issues. 
The system shows significant overall speedup as expected.

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.8.0-rc2 (root at debian) (gcc version 4.8.3 20140320 (prerelease) 
(Sourcery CodeBench Lite 2014.05-29) ) #23 PREEMPT Tue Aug 23 22:5 0:19 CEST 2016
[    0.000000] CPU: ARMv7-M [410fc271] revision 1 (ARMv7M), cr=00000000
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt:Machine model: SAME70-sampione board

So you can add my Tested-by.

Thanks for the patches!

Regards,
Andras Szemzo

[PATCH v2 0/8] ARM: V7M: Support caches

[Vladimir Murzin]

Hi

On 25/08/16 11:15, Szemz? Andr?s wrote:
> Hi,
> 
>> On 18 Aug 2016, at 16:57, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>>
>> Is it acceptable if patches hang on a list for awhile, so people (I'm
>> looking at Alex and  Szemz?) can test them?
>>
> 
> This is my first email to the list, so sorry If I make mistakes with my report,
> I still need to learn?
> 
> I have tested these patches on my custom board with ATMEL SAME70 armv7m SoC.
> 
> With default memory mapping configured MPU booting and rebooting works fine, I don?t see any issues. 
> The system shows significant overall speedup as expected.
> 
> [    0.000000] Booting Linux on physical CPU 0x0
> [    0.000000] Linux version 4.8.0-rc2 (root at debian) (gcc version 4.8.3 20140320 (prerelease) 
> (Sourcery CodeBench Lite 2014.05-29) ) #23 PREEMPT Tue Aug 23 22:5 0:19 CEST 2016
> [    0.000000] CPU: ARMv7-M [410fc271] revision 1 (ARMv7M), cr=00000000
> [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> [    0.000000] OF: fdt:Machine model: SAME70-sampione board
> 
> So you can add my Tested-by.
> 
> Thanks for the patches!

Thanks a lot for testing!

Cheers
Vladimir

> 
> Regards,
> Andras Szemzo
> 
> 

[PATCH v2 0/8] ARM: V7M: Support caches

[Joachim Eastwood]

Hi Vladimir,

On 18 August 2016 at 16:57, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
> On 18/08/16 15:53, Russell King - ARM Linux wrote:
>> On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
>>> This patch set allows M-class cpus benefit of optional cache support.
>>> It originally was written by Jonny, I've been keeping it locally mainly
>>> rebasing over Linux versions.
>>>
>>> The original idea behind patches was to reuse existing cache handling
>>> code from v7A/R with help of extra macros to factor out cache handling
>>> logic (v7M cache operations are provided via memory mapped interface
>>> rather than co-processor instructions).
>>> However, that idea was rejected and starting form this (v2) version
>>> V7M cache logic lives into file and macros to indirect memory-mapped
>>> operations stay there locally since they make it easier to follow the
>>> code.
>>>
>>> Along with the v7M cache support the first user (Cortex-M7) is
>>> introduced.
>>>
>>> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
>>> one showed significant boot speed-up.
>>
>>>From a quick read through, the approach looks sane, and I think I'm
>> now happy with these.
>>
>
> Thanks!
>
> Is it acceptable if patches hang on a list for awhile, so people (I'm
> looking at Alex and  Szemz?) can test them?

These patches doesn't seem to break anything on the cache-less
Cortex-M4 NXP LPC4357.

So FWIW:
Tested-by: Joachim Eastwood <manabian@gmail.com>


regards,
Joachim Eastwood

[PATCH v2 0/8] ARM: V7M: Support caches

[Vladimir Murzin]

Hi Joachim,

On 27/08/16 17:53, Joachim Eastwood wrote:
> Hi Vladimir,
> 
> On 18 August 2016 at 16:57, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>> On 18/08/16 15:53, Russell King - ARM Linux wrote:
>>> On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
>>>> This patch set allows M-class cpus benefit of optional cache support.
>>>> It originally was written by Jonny, I've been keeping it locally mainly
>>>> rebasing over Linux versions.
>>>>
>>>> The original idea behind patches was to reuse existing cache handling
>>>> code from v7A/R with help of extra macros to factor out cache handling
>>>> logic (v7M cache operations are provided via memory mapped interface
>>>> rather than co-processor instructions).
>>>> However, that idea was rejected and starting form this (v2) version
>>>> V7M cache logic lives into file and macros to indirect memory-mapped
>>>> operations stay there locally since they make it easier to follow the
>>>> code.
>>>>
>>>> Along with the v7M cache support the first user (Cortex-M7) is
>>>> introduced.
>>>>
>>>> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
>>>> one showed significant boot speed-up.
>>>
>>> >From a quick read through, the approach looks sane, and I think I'm
>>> now happy with these.
>>>
>>
>> Thanks!
>>
>> Is it acceptable if patches hang on a list for awhile, so people (I'm
>> looking at Alex and  Szemz?) can test them?
> 
> These patches doesn't seem to break anything on the cache-less
> Cortex-M4 NXP LPC4357.
> 

Great!

> So FWIW:
> Tested-by: Joachim Eastwood <manabian@gmail.com>
> 

Thanks a lot for testing!

Cheers
Vladimir

> 
> regards,
> Joachim Eastwood
> 
> 

[PATCH v2 0/8] ARM: V7M: Support caches

[Alexandre Torgue]

Hi Vladimir,

On 08/18/2016 04:57 PM, Vladimir Murzin wrote:
> On 18/08/16 15:53, Russell King - ARM Linux wrote:
>> On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
>>> This patch set allows M-class cpus benefit of optional cache support.
>>> It originally was written by Jonny, I've been keeping it locally mainly
>>> rebasing over Linux versions.
>>>
>>> The original idea behind patches was to reuse existing cache handling
>>> code from v7A/R with help of extra macros to factor out cache handling
>>> logic (v7M cache operations are provided via memory mapped interface
>>> rather than co-processor instructions).
>>> However, that idea was rejected and starting form this (v2) version
>>> V7M cache logic lives into file and macros to indirect memory-mapped
>>> operations stay there locally since they make it easier to follow the
>>> code.
>>>
>>> Along with the v7M cache support the first user (Cortex-M7) is
>>> introduced.
>>>
>>> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
>>> one showed significant boot speed-up.
>>
>> >From a quick read through, the approach looks sane, and I think I'm
>> now happy with these.
>>
>
> Thanks!
>
> Is it acceptable if patches hang on a list for awhile, so people (I'm
> looking at Alex and  Szemz?) can test them?

I just tested this v2 patch set. I don't see behavior issues.
You can add:
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>

Regards

Alex

>
> Vladimir
>
>> Thanks.
>>
>

[PATCH v2 0/8] ARM: V7M: Support caches

[Vladimir Murzin]

Hi Alex,

On 30/08/16 16:47, Alexandre Torgue wrote:
> Hi Vladimir,
> 
> On 08/18/2016 04:57 PM, Vladimir Murzin wrote:
>> On 18/08/16 15:53, Russell King - ARM Linux wrote:
>>> On Thu, Aug 18, 2016 at 01:45:52PM +0100, Vladimir Murzin wrote:
>>>> This patch set allows M-class cpus benefit of optional cache support.
>>>> It originally was written by Jonny, I've been keeping it locally mainly
>>>> rebasing over Linux versions.
>>>>
>>>> The original idea behind patches was to reuse existing cache handling
>>>> code from v7A/R with help of extra macros to factor out cache handling
>>>> logic (v7M cache operations are provided via memory mapped interface
>>>> rather than co-processor instructions).
>>>> However, that idea was rejected and starting form this (v2) version
>>>> V7M cache logic lives into file and macros to indirect memory-mapped
>>>> operations stay there locally since they make it easier to follow the
>>>> code.
>>>>
>>>> Along with the v7M cache support the first user (Cortex-M7) is
>>>> introduced.
>>>>
>>>> Patches were tested on MPS2 platform with Cortex-M3/M4/M7. The later
>>>> one showed significant boot speed-up.
>>>
>>> >From a quick read through, the approach looks sane, and I think I'm
>>> now happy with these.
>>>
>>
>> Thanks!
>>
>> Is it acceptable if patches hang on a list for awhile, so people (I'm
>> looking at Alex and  Szemz?) can test them?
> 
> I just tested this v2 patch set. I don't see behavior issues.
> You can add:
> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
> 

Thanks a lot for testing, Alex!

Cheers
Vladimir

> Regards
> 
> Alex
> 
>>
>> Vladimir
>>
>>> Thanks.
>>>
>>
> 
>