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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1vpW-00027f-Vq; Thu, 07 Mar 2019 16:25:10 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1vpT-0001sa-QC for linux-arm-kernel@lists.infradead.org; Thu, 07 Mar 2019 16:25:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DAEC980D; Thu, 7 Mar 2019 08:25:06 -0800 (PST) Received: from [10.1.196.92] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09F743F706; Thu, 7 Mar 2019 08:25:03 -0800 (PST) Subject: Re: [PATCH v2 01/10] ata: libahci: Ensure the host interrupt status bits are cleared To: Miquel Raynal , Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Mark Rutland , Jens Axboe , Hans de Goede , Thomas Gleixner References: <20190306102146.13005-1-miquel.raynal@bootlin.com> <20190306102146.13005-2-miquel.raynal@bootlin.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <20190306102146.13005-2-miquel.raynal@bootlin.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_082507_863666_F12B1D61 X-CRM114-Status: GOOD ( 19.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Baruch Siach , Antoine Tenart , Maxime Chevallier , Nadav Haklai , linux-ide@vger.kernel.org, Thomas Petazzoni , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 06/03/2019 10:21, Miquel Raynal wrote: > ahci_multi_irqs_intr_hard() is going to be used as interrupt handler > to support SATA per-port interrupts. The current logic is to check and > clear the SATA port interrupt status register only. To avoid spurious > IRQs and interrupt storms, it will be needed to clear the port > interrupt bit in the host interrupt status register as well. > > Signed-off-by: Miquel Raynal > --- > drivers/ata/libahci.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c > index b5f57c69c487..66d4906a5013 100644 > --- a/drivers/ata/libahci.c > +++ b/drivers/ata/libahci.c > @@ -1912,7 +1912,10 @@ static void ahci_port_intr(struct ata_port *ap) > static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) > { > struct ata_port *ap = dev_instance; > + struct ata_host *host = ap->host; > + struct ahci_host_priv *hpriv = host->private_data; > void __iomem *port_mmio = ahci_port_base(ap); > + void __iomem *mmio = hpriv->mmio; > u32 status; > > VPRINTK("ENTER\n"); > @@ -1924,6 +1927,10 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) > ahci_handle_port_interrupt(ap, port_mmio, status); > spin_unlock(ap->lock); > > + spin_lock(&host->lock); > + writel(BIT(ap->port_no), mmio + HOST_IRQ_STAT); > + spin_unlock(&host->lock); What's not clear here is under which circumstances this is required. This write should be atomic (if it isn't, you have bigger problems), and it is at best unclear what you're avoiding by taking the host lock. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel