linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: vladimir.murzin@arm.com (Vladimir Murzin)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 7/8] KVM: arm64: vgic-its: fix compatability with 32-bit
Date: Fri, 21 Oct 2016 12:19:31 +0100	[thread overview]
Message-ID: <5809F9C3.7020309@arm.com> (raw)
In-Reply-To: <5ea0ecc0-edb1-f770-16f3-7c48dbdb5c29@arm.com>

On 21/10/16 10:49, Andre Przywara wrote:
> Hi,
> 
> On 21/10/16 10:36, Vladimir Murzin wrote:
>> Evaluate GITS_BASER_ENTRY_SIZE once as an int data (GITS_BASER<n>'s
>> Entry Size is 5-bit wide only), so when used as divider no reference
>> to __aeabi_uldivmod is generated when build for AArch32.
>>
>> Use unsigned long long for GITS_BASER_PAGE_SIZE_* since they are
>> used in conjunction with 64-bit data.
>>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> 
> Looks good to me, thanks for fixing this!
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks!

Vladimir

> 
> Cheers,
> Andre.
> 
>> ---
>>  include/linux/irqchip/arm-gic-v3.h |    8 ++++----
>>  virt/kvm/arm/vgic/vgic-its.c       |   11 ++++++-----
>>  2 files changed, 10 insertions(+), 9 deletions(-)
>>
>> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
>> index 5118d3a..e808f8a 100644
>> --- a/include/linux/irqchip/arm-gic-v3.h
>> +++ b/include/linux/irqchip/arm-gic-v3.h
>> @@ -295,10 +295,10 @@
>>  #define GITS_BASER_InnerShareable					\
>>  	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
>>  #define GITS_BASER_PAGE_SIZE_SHIFT	(8)
>> -#define GITS_BASER_PAGE_SIZE_4K		(0UL << GITS_BASER_PAGE_SIZE_SHIFT)
>> -#define GITS_BASER_PAGE_SIZE_16K	(1UL << GITS_BASER_PAGE_SIZE_SHIFT)
>> -#define GITS_BASER_PAGE_SIZE_64K	(2UL << GITS_BASER_PAGE_SIZE_SHIFT)
>> -#define GITS_BASER_PAGE_SIZE_MASK	(3UL << GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_4K		(0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_16K	(1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_64K	(2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_MASK	(3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
>>  #define GITS_BASER_PAGES_MAX		256
>>  #define GITS_BASER_PAGES_SHIFT		(0)
>>  #define GITS_BASER_NR_PAGES(r)		(((r) & 0xff) + 1)
>> diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
>> index 4660a7d..8c2b3cd 100644
>> --- a/virt/kvm/arm/vgic/vgic-its.c
>> +++ b/virt/kvm/arm/vgic/vgic-its.c
>> @@ -632,21 +632,22 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
>>  	int index;
>>  	u64 indirect_ptr;
>>  	gfn_t gfn;
>> +	int esz = GITS_BASER_ENTRY_SIZE(baser);
>>  
>>  	if (!(baser & GITS_BASER_INDIRECT)) {
>>  		phys_addr_t addr;
>>  
>> -		if (id >= (l1_tbl_size / GITS_BASER_ENTRY_SIZE(baser)))
>> +		if (id >= (l1_tbl_size / esz))
>>  			return false;
>>  
>> -		addr = BASER_ADDRESS(baser) + id * GITS_BASER_ENTRY_SIZE(baser);
>> +		addr = BASER_ADDRESS(baser) + id * esz;
>>  		gfn = addr >> PAGE_SHIFT;
>>  
>>  		return kvm_is_visible_gfn(its->dev->kvm, gfn);
>>  	}
>>  
>>  	/* calculate and check the index into the 1st level */
>> -	index = id / (SZ_64K / GITS_BASER_ENTRY_SIZE(baser));
>> +	index = id / (SZ_64K / esz);
>>  	if (index >= (l1_tbl_size / sizeof(u64)))
>>  		return false;
>>  
>> @@ -670,8 +671,8 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
>>  	indirect_ptr &= GENMASK_ULL(51, 16);
>>  
>>  	/* Find the address of the actual entry */
>> -	index = id % (SZ_64K / GITS_BASER_ENTRY_SIZE(baser));
>> -	indirect_ptr += index * GITS_BASER_ENTRY_SIZE(baser);
>> +	index = id % (SZ_64K / esz);
>> +	indirect_ptr += index * esz;
>>  	gfn = indirect_ptr >> PAGE_SHIFT;
>>  
>>  	return kvm_is_visible_gfn(its->dev->kvm, gfn);
>>
> 

  reply	other threads:[~2016-10-21 11:19 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-21  9:36 [RFC PATCH 0/8] Support GICv3 ITS and vITS in 32-bit mode Vladimir Murzin
2016-10-21  9:36 ` [RFC PATCH 1/8] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility Vladimir Murzin
2016-10-21  9:36 ` [RFC PATCH 2/8] irqchip/gic-v3-its: narrow down Entry Size when used as a divider Vladimir Murzin
2016-10-21  9:36 ` [RFC PATCH 3/8] irqchip/gicv3-its: specialise flush_dcache operation Vladimir Murzin
2016-10-21  9:36 ` [RFC PATCH 4/8] irqchip/gicv3-its: specialise readq and writeq accesses Vladimir Murzin
2016-10-22 15:43   ` Marc Zyngier
2016-10-21  9:36 ` [RFC PATCH 5/8] ARM: gic-v3-its: Add 32bit support to GICv3 ITS Vladimir Murzin
2016-10-21  9:36 ` [RFC PATCH 6/8] ARM: virt: select ARM_GIC_V3_ITS Vladimir Murzin
2016-10-21  9:36 ` [RFC PATCH 7/8] KVM: arm64: vgic-its: fix compatability with 32-bit Vladimir Murzin
2016-10-21  9:49   ` Andre Przywara
2016-10-21 11:19     ` Vladimir Murzin [this message]
2016-10-21  9:36 ` [RFC PATCH 8/8] ARM: KVM: Support vGICv3 ITS Vladimir Murzin
2016-10-21 11:02   ` Andre Przywara
2016-10-21 11:20     ` Vladimir Murzin
2016-10-22 15:55 ` [RFC PATCH 0/8] Support GICv3 ITS and vITS in 32-bit mode Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5809F9C3.7020309@arm.com \
    --to=vladimir.murzin@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).