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Sun, 20 Sep 2026 04:08:38 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface MIME-Version: 1.0 X-ThreadId: AzgOxjlYMeWB Date: Sun, 20 Sep 2026 10:08:18 +0200 From: "Arnd Bergmann" To: "Qingfang Deng" , "Catalin Marinas" , "Will Deacon" , "Mark Rutland" , "Anshuman Khandual" , "Vikram Sethi" , "Mike Rapoport" , "Shanker Donthineni" , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-Arch Message-Id: <5847c824-8d69-4d02-af2f-896bf47f0732@app.fastmail.com> In-Reply-To: <20260920014357.7069-3-qingfang.deng@linux.dev> References: <20260920014357.7069-1-qingfang.deng@linux.dev> <20260920014357.7069-3-qingfang.deng@linux.dev> Subject: Re: [PATCH v2 3/3] arm64: use generic MMIO accessors Content-Type: text/plain Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260920_010849_094321_C0F9DD62 X-CRM114-Status: UNSURE ( 8.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Sep 20, 2026, at 03:43, Qingfang Deng wrote: > Use the generic raw write accessors in place of the inline assembly > stores. Include asm-generic/mmio.h after the arm64 ordering hooks so > these accessors are also available to the write-combining helpers > before asm-generic/io.h is included. > > Retain the raw read overrides when either the Cortex-A57 erratum 832075 > or NVIDIA Olympus erratum 1027 workaround is configured. This preserves > the alternative-patched load-acquire instructions and pre-load barriers. > Use generic raw reads when neither workaround is enabled. > > Assisted-by: Codex:gpt-6-astra > Signed-off-by: Qingfang Deng Sorry, this is no good, we need the compiler to issue the exact instructions from the inline asm here, both in order to guarantee these can be virtualized, and to prevent it from splitting up larger register accesses into byte load/store on unaligned pointers. Arnd