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Thu, 09 Jun 2022 14:14:19 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E7E4110002A; Thu, 9 Jun 2022 14:14:17 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id DF6D62171F4; Thu, 9 Jun 2022 14:14:17 +0200 (CEST) Received: from [10.48.1.102] (10.75.127.47) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Thu, 9 Jun 2022 14:14:16 +0200 Message-ID: <587eed11-8418-24a2-e8f7-d624ec570ebe@foss.st.com> Date: Thu, 9 Jun 2022 14:14:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] iio: adc: stm32: fix maximum clock rate for stm32mp15x Content-Language: en-US To: Olivier Moysan , Alexandre Torgue , Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , Paul Cercueil CC: , , , References: <20220609095234.375925-1-olivier.moysan@foss.st.com> From: Fabrice Gasnier In-Reply-To: <20220609095234.375925-1-olivier.moysan@foss.st.com> X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-09_09,2022-06-09_01,2022-02-23_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220609_051443_788943_BA625E03 X-CRM114-Status: GOOD ( 17.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/9/22 11:52, Olivier Moysan wrote: > Change maximum STM32 ADC input clock rate to 36MHz, as specified > in STM32MP15x datasheets. > > Fixes: d58c67d1d851 ("iio: adc: stm32-adc: add support for STM32MP1") > > Signed-off-by: Olivier Moysan Hi Olivier, You can add my: Reviewed-by: Fabrice Gasnier Thanks, Fabrice > --- > drivers/iio/adc/stm32-adc-core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c > index 142656232157..ce1a63a82034 100644 > --- a/drivers/iio/adc/stm32-adc-core.c > +++ b/drivers/iio/adc/stm32-adc-core.c > @@ -805,7 +805,7 @@ static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { > static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { > .regs = &stm32h7_adc_common_regs, > .clk_sel = stm32h7_adc_clk_sel, > - .max_clk_rate_hz = 40000000, > + .max_clk_rate_hz = 36000000, > .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, > .num_irqs = 2, > }; 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