From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41B09CE7AFF for ; Fri, 6 Sep 2024 10:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:References:CC:To: Subject:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3U6Kga7Pep+QfKshoD1SAh2i5ibTgL6bDAL0CyNQGZA=; b=fH2cyqkDeATtXCj/rDYuExidZE sGGlCHjaVMaXDDcGKLAIbD2EC8D6DBEF3rv4+WCTGjl2OWi7Gx18pzjtrM23XlfNUmm1crv5QsJLw t5vWfrlLB4ydxiOYgqXEJNBWJrww9DIT6O2GJUh3DOTBYP2oyLhLdCEaieKDY9gK41ME+mMDYaiRI 08cIL/nhtaphOSPFIcOAFxXAOhiJCOwj8dvwtFvGAwohGHq1ROdmhfoJHFhgKiDVN0/JjBQijZ98F Vk+vRdMoPd0h3VgzTdFyz3kzYHqGIGdvWVMwqyiYQUP2VZjMSHEIMPminAFm8DS+QH54IwINPKAwA XKzPSyUg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1smWgq-0000000Brym-2Jma; Fri, 06 Sep 2024 10:59:44 +0000 Received: from szxga08-in.huawei.com ([45.249.212.255]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1smWfp-0000000Brl4-3Xpy for linux-arm-kernel@lists.infradead.org; Fri, 06 Sep 2024 10:58:44 +0000 Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4X0Y8t1Gwvz1P9J7; Fri, 6 Sep 2024 18:57:34 +0800 (CST) Received: from kwepemf100009.china.huawei.com (unknown [7.202.181.223]) by mail.maildlp.com (Postfix) with ESMTPS id 37BD614011A; Fri, 6 Sep 2024 18:58:34 +0800 (CST) Received: from [10.67.121.162] (10.67.121.162) by kwepemf100009.china.huawei.com (7.202.181.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 6 Sep 2024 18:58:33 +0800 Subject: Re: [PATCH] arm64: Add ARM64_HAS_LSE2 CPU capability To: Mark Rutland CC: , , , , , References: <20240906090812.249473-1-tiantao6@hisilicon.com> From: "tiantao (H)" Message-ID: <587f7c84-cdfc-b348-4cd0-1015adad2cca@hisilicon.com> Date: Fri, 6 Sep 2024 18:58:19 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.121.162] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemf100009.china.huawei.com (7.202.181.223) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240906_035842_416872_FC5C75F9 X-CRM114-Status: GOOD ( 22.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 在 2024/9/6 17:44, Mark Rutland 写道: > On Fri, Sep 06, 2024 at 05:08:12PM +0800, Tian Tao wrote: >> When FEAT_LSE2 is implemented and Bit 6 of sctlr_elx is nAA, the >> full name of the Not-aligned access. nAA bit has two values: >> 0b0 Unaligned accesses by the specified instructions generate an >> Alignment fault. >> 0b1 Unaligned accesses by the specified instructions do not generate >> an Alignment fault. >> >> this patch sets the nAA bit to 1,The following instructions will not >> generate an Alignment fault if all bytes being accessed are not within >> a single 16-byte quantity: >> • LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH,LDLAR, >> LDLARH. >> • STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH >> >> Signed-off-by: Tian Tao > What is going to depend on this? Nothing in the kernel depends on being > able to make unaligned accesses with these instructions, and (since you > haven't added a HWCAP), userspace has no idea that these accesses won't > generate an alignment fault. > > Mark. I've come across a situation where the simplified code is as follows:  long  address = (long) mmap(NULL,1024*1024*2,PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS,-1,0); long new_address = address + 9;  long *p = (long*) new_address;  long v = -1;  __atomic_store(p, &v, __ATOMIC_RELEASE); coredump occurs after executing __atomic_store, but the user code can't be changed, so I'm trying to enable NAA to solve this problem. >> --- >> arch/arm64/Kconfig | 10 ++++++++++ >> arch/arm64/include/asm/sysreg.h | 1 + >> arch/arm64/kernel/cpufeature.c | 18 ++++++++++++++++++ >> arch/arm64/tools/cpucaps | 1 + >> 4 files changed, 30 insertions(+) >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 77d7ef0b16c2..7afe73ebcd79 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -2023,6 +2023,16 @@ config ARM64_TLB_RANGE >> The feature introduces new assembly instructions, and they were >> support when binutils >= 2.30. >> >> +config ARM64_LSE2_NAA >> + bool "Enable support for not-aligned access" >> + depends on AS_HAS_ARMV8_4 >> + help >> + LSE2 is an extension to the original LSE (Large System Extensions) feature, >> + introduced in ARMv8.4. >> + >> + Enable this feature will not generate an Alignment fault if all bytes being >> + accessed are not within a single 16-byte quantity. >> + >> endmenu # "ARMv8.4 architectural features" >> >> menu "ARMv8.5 architectural features" >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 8cced8aa75a9..42e3a1959aa8 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -854,6 +854,7 @@ >> #define SCTLR_ELx_ENDB (BIT(13)) >> #define SCTLR_ELx_I (BIT(12)) >> #define SCTLR_ELx_EOS (BIT(11)) >> +#define SCTLR_ELx_nAA (BIT(6)) >> #define SCTLR_ELx_SA (BIT(3)) >> #define SCTLR_ELx_C (BIT(2)) >> #define SCTLR_ELx_A (BIT(1)) >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 646ecd3069fd..558869a7c7f0 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -2299,6 +2299,14 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) >> } >> #endif /* CONFIG_ARM64_MTE */ >> >> +#ifdef CONFIG_ARM64_LSE2_NAA >> +static void cpu_enable_lse2(const struct arm64_cpu_capabilities *__unused) >> +{ >> + sysreg_clear_set(sctlr_el2, SCTLR_ELx_nAA, SCTLR_ELx_nAA); >> + isb(); >> +} >> +#endif >> + >> static void user_feature_fixup(void) >> { >> if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { >> @@ -2427,6 +2435,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { >> ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) >> }, >> #endif /* CONFIG_ARM64_LSE_ATOMICS */ >> +#ifdef CONFIG_ARM64_LSE2_NAA >> + { >> + .desc = "Support for not-aligned access", >> + .capability = ARM64_HAS_LSE2, >> + .type = ARM64_CPUCAP_SYSTEM_FEATURE, >> + .matches = has_cpuid_feature, >> + .cpu_enable = cpu_enable_lse2, >> + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, AT, IMP) >> + }, >> +#endif >> { >> .desc = "Virtualization Host Extensions", >> .capability = ARM64_HAS_VIRT_HOST_EXTN, >> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >> index ac3429d892b9..0c7c0a293574 100644 >> --- a/arch/arm64/tools/cpucaps >> +++ b/arch/arm64/tools/cpucaps >> @@ -41,6 +41,7 @@ HAS_HCX >> HAS_LDAPR >> HAS_LPA2 >> HAS_LSE_ATOMICS >> +HAS_LSE2 >> HAS_MOPS >> HAS_NESTED_VIRT >> HAS_PAN >> -- >> 2.33.0 >> >> > . >