[PATCH 0/5] ARM: shmobile: r8a7790: enable IIC(B) cores

[PATCH 0/5] ARM: shmobile: r8a7790: enable IIC(B) cores

[Wolfram Sang]

This series allows r8a7790 boards to use the alternative IIC(B) controller
handled by the i2c-sh_mobile driver. Since both i2c cores always use the same
pins only in a different function group, you can easily use this or that core
for your devices. For that reason, there is currently no enablement on the
Lager board, since it needs discussion which core we want to have on which bus.
sh_mobile seems more stable currently, so I'd vote for that.

Please review and apply if no issues found.

Thanks,

   Wolfram


Wolfram Sang (5):
  pinctrl: pfc: r8a7790: add i2c0 muxing
  pinctrl: pfc: r8a7790: add mux data for IIC(B) cores
  ARM: shmobile: r8a7790: add IIC0-2 clock macros
  ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi
  ARM: shmobile: r8a7790: add IIC(B) cores to dtsi

 arch/arm/boot/dts/r8a7790.dtsi            |  71 +++++++++++++---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c      | 136 +++++++++++++++++++++++++++++-
 include/dt-bindings/clock/r8a7790-clock.h |   3 +
 3 files changed, 196 insertions(+), 14 deletions(-)

-- 
1.9.0

[PATCH 1/5] pinctrl: pfc: r8a7790: add i2c0 muxing

[Wolfram Sang]

From: Wolfram Sang <wsa@sang-engineering.com>

Add the muxing for the last missing i2c rcar core.

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index c381ae63c508..bd21022cf9bf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -782,6 +782,7 @@ enum {
 	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 	TCLK1_B_MARK,
 
+	I2C0_SCL_MARK, I2C0_SDA_MARK,
 	I2C3_SCL_MARK, I2C3_SDA_MARK,
 	PINMUX_MARK_END,
 };
@@ -1722,6 +1723,9 @@ static const u16 pinmux_data[] = {
 	PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
 	PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
 
+	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
+	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
+
 	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
 	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
 };
@@ -1735,6 +1739,8 @@ static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 
 	/* Pins not associated with a GPIO port */
+	SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
+	SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
 	SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
 	SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
 };
@@ -2054,6 +2060,14 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
 static const unsigned int hscif1_ctrl_b_mux[] = {
 	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
 };
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+	/* SCL, SDA */
+	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
+};
+static const unsigned int i2c0_mux[] = {
+	I2C0_SCL_MARK, I2C0_SDA_MARK,
+};
 /* - I2C1 ------------------------------------------------------------------- */
 static const unsigned int i2c1_pins[] = {
 	/* SCL, SDA */
@@ -3626,6 +3640,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif1_data_b),
 	SH_PFC_PIN_GROUP(hscif1_clk_b),
 	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+	SH_PFC_PIN_GROUP(i2c0),
 	SH_PFC_PIN_GROUP(i2c1),
 	SH_PFC_PIN_GROUP(i2c1_b),
 	SH_PFC_PIN_GROUP(i2c1_c),
@@ -3895,6 +3910,10 @@ static const char * const hscif1_groups[] = {
 	"hscif1_ctrl_b",
 };
 
+static const char * const i2c0_groups[] = {
+	"i2c0",
+};
+
 static const char * const i2c1_groups[] = {
 	"i2c1",
 	"i2c1_b",
@@ -4203,6 +4222,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(eth),
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
+	SH_PFC_FUNCTION(i2c0),
 	SH_PFC_FUNCTION(i2c1),
 	SH_PFC_FUNCTION(i2c2),
 	SH_PFC_FUNCTION(i2c3),
-- 
1.9.0

[PATCH 1/5] pinctrl: pfc: r8a7790: add i2c0 muxing

[Laurent Pinchart]

Hi Wolfram,

Thank you for the patch.

On Tuesday 11 March 2014 22:24:34 Wolfram Sang wrote:
> From: Wolfram Sang <wsa@sang-engineering.com>
> 
> Add the muxing for the last missing i2c rcar core.
> 
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c381ae63c508..bd21022cf9bf
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> @@ -782,6 +782,7 @@ enum {
>  	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
>  	TCLK1_B_MARK,
> 
> +	I2C0_SCL_MARK, I2C0_SDA_MARK,
>  	I2C3_SCL_MARK, I2C3_SDA_MARK,
>  	PINMUX_MARK_END,
>  };
> @@ -1722,6 +1723,9 @@ static const u16 pinmux_data[] = {
>  	PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
>  	PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
> 
> +	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
> +	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
> +
>  	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
>  	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
>  };
> @@ -1735,6 +1739,8 @@ static const struct sh_pfc_pin pinmux_pins[] = {
>  	PINMUX_GPIO_GP_ALL(),
> 
>  	/* Pins not associated with a GPIO port */
> +	SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
> +	SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),

I would swap those two lines to keep pin entries sorted alphabetically.

>  	SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
>  	SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),

I realize that those two lines should be swapped as well. You could do so in 
the same patch.

>  };
> @@ -2054,6 +2060,14 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
>  static const unsigned int hscif1_ctrl_b_mux[] = {
>  	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
>  };
> +/* - I2C0
> ------------------------------------------------------------------- */
> +static const unsigned int i2c0_pins[] = {
> +	/* SCL, SDA */
> +	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
> +};
> +static const unsigned int i2c0_mux[] = {
> +	I2C0_SCL_MARK, I2C0_SDA_MARK,
> +};
>  /* - I2C1
> ------------------------------------------------------------------- */
> static const unsigned int i2c1_pins[] = {
>  	/* SCL, SDA */
> @@ -3626,6 +3640,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] =
> { SH_PFC_PIN_GROUP(hscif1_data_b),
>  	SH_PFC_PIN_GROUP(hscif1_clk_b),
>  	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
> +	SH_PFC_PIN_GROUP(i2c0),
>  	SH_PFC_PIN_GROUP(i2c1),
>  	SH_PFC_PIN_GROUP(i2c1_b),
>  	SH_PFC_PIN_GROUP(i2c1_c),
> @@ -3895,6 +3910,10 @@ static const char * const hscif1_groups[] = {
>  	"hscif1_ctrl_b",
>  };
> 
> +static const char * const i2c0_groups[] = {
> +	"i2c0",
> +};
> +
>  static const char * const i2c1_groups[] = {
>  	"i2c1",
>  	"i2c1_b",
> @@ -4203,6 +4222,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(eth),
>  	SH_PFC_FUNCTION(hscif0),
>  	SH_PFC_FUNCTION(hscif1),
> +	SH_PFC_FUNCTION(i2c0),
>  	SH_PFC_FUNCTION(i2c1),
>  	SH_PFC_FUNCTION(i2c2),
>  	SH_PFC_FUNCTION(i2c3),

-- 
Regards,

Laurent Pinchart

[PATCH 2/5] pinctrl: pfc: r8a7790: add mux data for IIC(B) cores

[Wolfram Sang]

From: Wolfram Sang <wsa@sang-engineering.com>

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 118 ++++++++++++++++++++++++++++++++++-
 1 file changed, 116 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index bd21022cf9bf..857d5c3d2fa8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -782,8 +782,8 @@ enum {
 	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 	TCLK1_B_MARK,
 
-	I2C0_SCL_MARK, I2C0_SDA_MARK,
-	I2C3_SCL_MARK, I2C3_SDA_MARK,
+	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
+	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
 	PINMUX_MARK_END,
 };
 
@@ -1723,9 +1723,13 @@ static const u16 pinmux_data[] = {
 	PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
 	PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
 
+	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
+	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
 	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
 	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
 
+	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
+	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
 	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
 	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
 };
@@ -2134,6 +2138,80 @@ static const unsigned int i2c3_pins[] = {
 static const unsigned int i2c3_mux[] = {
 	I2C3_SCL_MARK, I2C3_SDA_MARK,
 };
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+	/* SCL, SDA */
+	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
+};
+static const unsigned int i2c4_mux[] = {
+	IIC0_SCL_MARK, IIC0_SDA_MARK,
+};
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int i2c5_mux[] = {
+	IIC1_SCL_MARK, IIC1_SDA_MARK,
+};
+static const unsigned int i2c5_b_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int i2c5_b_mux[] = {
+	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
+};
+static const unsigned int i2c5_c_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int i2c5_c_mux[] = {
+	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
+};
+/* - I2C6 ------------------------------------------------------------------- */
+static const unsigned int i2c6_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int i2c6_mux[] = {
+	IIC2_SCL_MARK, IIC2_SDA_MARK,
+};
+static const unsigned int i2c6_b_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int i2c6_b_mux[] = {
+	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
+};
+static const unsigned int i2c6_c_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int i2c6_c_mux[] = {
+	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
+};
+static const unsigned int i2c6_d_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c6_d_mux[] = {
+	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
+};
+static const unsigned int i2c6_e_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+static const unsigned int i2c6_e_mux[] = {
+	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
+};
+/* - I2C7 ------------------------------------------------------------------- */
+static const unsigned int i2c7_pins[] = {
+/* SCL, SDA */
+	PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
+};
+static const unsigned int i2c7_mux[] = {
+	IIC3_SCL_MARK, IIC3_SDA_MARK,
+};
 /* - INTC ------------------------------------------------------------------- */
 static const unsigned int intc_irq0_pins[] = {
 	/* IRQ */
@@ -3650,6 +3728,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(i2c2_d),
 	SH_PFC_PIN_GROUP(i2c2_e),
 	SH_PFC_PIN_GROUP(i2c3),
+	SH_PFC_PIN_GROUP(i2c4),
+	SH_PFC_PIN_GROUP(i2c5),
+	SH_PFC_PIN_GROUP(i2c5_b),
+	SH_PFC_PIN_GROUP(i2c5_c),
+	SH_PFC_PIN_GROUP(i2c6),
+	SH_PFC_PIN_GROUP(i2c6_b),
+	SH_PFC_PIN_GROUP(i2c6_c),
+	SH_PFC_PIN_GROUP(i2c6_d),
+	SH_PFC_PIN_GROUP(i2c6_e),
+	SH_PFC_PIN_GROUP(i2c7),
 	SH_PFC_PIN_GROUP(intc_irq0),
 	SH_PFC_PIN_GROUP(intc_irq1),
 	SH_PFC_PIN_GROUP(intc_irq2),
@@ -3932,6 +4020,28 @@ static const char * const i2c3_groups[] = {
 	"i2c3",
 };
 
+static const char * const i2c4_groups[] = {
+	"i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+	"i2c5",
+	"i2c5_b",
+	"i2c5_c",
+};
+
+static const char * const i2c6_groups[] = {
+	"i2c6",
+	"i2c6_b",
+	"i2c6_c",
+	"i2c6_d",
+	"i2c6_e",
+};
+
+static const char * const i2c7_groups[] = {
+	"i2c7",
+};
+
 static const char * const intc_groups[] = {
 	"intc_irq0",
 	"intc_irq1",
@@ -4226,6 +4336,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(i2c1),
 	SH_PFC_FUNCTION(i2c2),
 	SH_PFC_FUNCTION(i2c3),
+	SH_PFC_FUNCTION(i2c4),
+	SH_PFC_FUNCTION(i2c5),
+	SH_PFC_FUNCTION(i2c6),
+	SH_PFC_FUNCTION(i2c7),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(mmc1),
-- 
1.9.0

[PATCH 2/5] pinctrl: pfc: r8a7790: add mux data for IIC(B) cores

[Laurent Pinchart]

Hi Wolfram,

Thank you for the patch.

On Tuesday 11 March 2014 22:24:35 Wolfram Sang wrote:
> From: Wolfram Sang <wsa@sang-engineering.com>
> 
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 118 +++++++++++++++++++++++++++++++-
>  1 file changed, 116 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index bd21022cf9bf..857d5c3d2fa8
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
> @@ -782,8 +782,8 @@ enum {
>  	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
>  	TCLK1_B_MARK,
> 
> -	I2C0_SCL_MARK, I2C0_SDA_MARK,
> -	I2C3_SCL_MARK, I2C3_SDA_MARK,
> +	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
> +	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
>  	PINMUX_MARK_END,
>  };
> 
> @@ -1723,9 +1723,13 @@ static const u16 pinmux_data[] = {
>  	PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
>  	PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
> 
> +	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
> +	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
>  	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
>  	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
> 
> +	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
> +	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
>  	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
>  	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
>  };
> @@ -2134,6 +2138,80 @@ static const unsigned int i2c3_pins[] = {
>  static const unsigned int i2c3_mux[] = {
>  	I2C3_SCL_MARK, I2C3_SDA_MARK,
>  };
> +/* - I2C4
> ------------------------------------------------------------------- */

What about calling the groups iic0-iic3 to match the names from the datasheet 
?

The rest of the patch looks good to me.

> +static const unsigned int i2c4_pins[] = {
> +	/* SCL, SDA */
> +	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
> +};
> +static const unsigned int i2c4_mux[] = {
> +	IIC0_SCL_MARK, IIC0_SDA_MARK,
> +};
> +/* - I2C5
> ------------------------------------------------------------------- */
> +static const unsigned int i2c5_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
> +};
> +static const unsigned int i2c5_mux[] = {
> +	IIC1_SCL_MARK, IIC1_SDA_MARK,
> +};
> +static const unsigned int i2c5_b_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> +};
> +static const unsigned int i2c5_b_mux[] = {
> +	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
> +};
> +static const unsigned int i2c5_c_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
> +};
> +static const unsigned int i2c5_c_mux[] = {
> +	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
> +};
> +/* - I2C6
> ------------------------------------------------------------------- */
> +static const unsigned int i2c6_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
> +};
> +static const unsigned int i2c6_mux[] = {
> +	IIC2_SCL_MARK, IIC2_SDA_MARK,
> +};
> +static const unsigned int i2c6_b_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
> +};
> +static const unsigned int i2c6_b_mux[] = {
> +	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
> +};
> +static const unsigned int i2c6_c_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
> +};
> +static const unsigned int i2c6_c_mux[] = {
> +	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
> +};
> +static const unsigned int i2c6_d_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
> +};
> +static const unsigned int i2c6_d_mux[] = {
> +	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
> +};
> +static const unsigned int i2c6_e_pins[] = {
> +	/* SCL, SDA */
> +	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
> +};
> +static const unsigned int i2c6_e_mux[] = {
> +	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
> +};
> +/* - I2C7
> ------------------------------------------------------------------- */
> +static const unsigned int i2c7_pins[] = {
> +/* SCL, SDA */
> +	PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
> +};
> +static const unsigned int i2c7_mux[] = {
> +	IIC3_SCL_MARK, IIC3_SDA_MARK,
> +};
>  /* - INTC
> ------------------------------------------------------------------- */
> static const unsigned int intc_irq0_pins[] = {
>  	/* IRQ */
> @@ -3650,6 +3728,16 @@ static const struct sh_pfc_pin_group pinmux_groups[]
> = { SH_PFC_PIN_GROUP(i2c2_d),
>  	SH_PFC_PIN_GROUP(i2c2_e),
>  	SH_PFC_PIN_GROUP(i2c3),
> +	SH_PFC_PIN_GROUP(i2c4),
> +	SH_PFC_PIN_GROUP(i2c5),
> +	SH_PFC_PIN_GROUP(i2c5_b),
> +	SH_PFC_PIN_GROUP(i2c5_c),
> +	SH_PFC_PIN_GROUP(i2c6),
> +	SH_PFC_PIN_GROUP(i2c6_b),
> +	SH_PFC_PIN_GROUP(i2c6_c),
> +	SH_PFC_PIN_GROUP(i2c6_d),
> +	SH_PFC_PIN_GROUP(i2c6_e),
> +	SH_PFC_PIN_GROUP(i2c7),
>  	SH_PFC_PIN_GROUP(intc_irq0),
>  	SH_PFC_PIN_GROUP(intc_irq1),
>  	SH_PFC_PIN_GROUP(intc_irq2),
> @@ -3932,6 +4020,28 @@ static const char * const i2c3_groups[] = {
>  	"i2c3",
>  };
> 
> +static const char * const i2c4_groups[] = {
> +	"i2c4",
> +};
> +
> +static const char * const i2c5_groups[] = {
> +	"i2c5",
> +	"i2c5_b",
> +	"i2c5_c",
> +};
> +
> +static const char * const i2c6_groups[] = {
> +	"i2c6",
> +	"i2c6_b",
> +	"i2c6_c",
> +	"i2c6_d",
> +	"i2c6_e",
> +};
> +
> +static const char * const i2c7_groups[] = {
> +	"i2c7",
> +};
> +
>  static const char * const intc_groups[] = {
>  	"intc_irq0",
>  	"intc_irq1",
> @@ -4226,6 +4336,10 @@ static const struct sh_pfc_function
> pinmux_functions[] = { SH_PFC_FUNCTION(i2c1),
>  	SH_PFC_FUNCTION(i2c2),
>  	SH_PFC_FUNCTION(i2c3),
> +	SH_PFC_FUNCTION(i2c4),
> +	SH_PFC_FUNCTION(i2c5),
> +	SH_PFC_FUNCTION(i2c6),
> +	SH_PFC_FUNCTION(i2c7),
>  	SH_PFC_FUNCTION(intc),
>  	SH_PFC_FUNCTION(mmc0),
>  	SH_PFC_FUNCTION(mmc1),

-- 
Regards,

Laurent Pinchart

[PATCH 3/5] ARM: shmobile: r8a7790: add IIC0-2 clock macros

[Wolfram Sang]

From: Wolfram Sang <wsa@sang-engineering.com>

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
---
 include/dt-bindings/clock/r8a7790-clock.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 6548a5fbcf4a..4d3e935b3f1b 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -50,6 +50,7 @@
 #define R8A7790_CLK_SYS_DMAC0		19
 
 /* MSTP3 */
+#define R8A7790_CLK_IIC2		0
 #define R8A7790_CLK_TPU0		4
 #define R8A7790_CLK_MMCIF1		5
 #define R8A7790_CLK_SDHI3		11
@@ -57,6 +58,8 @@
 #define R8A7790_CLK_SDHI1		13
 #define R8A7790_CLK_SDHI0		14
 #define R8A7790_CLK_MMCIF0		15
+#define R8A7790_CLK_IIC0		18
+#define R8A7790_CLK_IIC1		23
 #define R8A7790_CLK_SSUSB		28
 #define R8A7790_CLK_CMT1		29
 #define R8A7790_CLK_USBDMAC0		30
-- 
1.9.0

[PATCH 3/5] ARM: shmobile: r8a7790: add IIC0-2 clock macros

[Laurent Pinchart]

Hi Wolfram,

Thank you for the patch.

On Tuesday 11 March 2014 22:24:36 Wolfram Sang wrote:
> From: Wolfram Sang <wsa@sang-engineering.com>
> 
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
>  include/dt-bindings/clock/r8a7790-clock.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/r8a7790-clock.h
> b/include/dt-bindings/clock/r8a7790-clock.h index
> 6548a5fbcf4a..4d3e935b3f1b 100644
> --- a/include/dt-bindings/clock/r8a7790-clock.h
> +++ b/include/dt-bindings/clock/r8a7790-clock.h
> @@ -50,6 +50,7 @@
>  #define R8A7790_CLK_SYS_DMAC0		19
> 
>  /* MSTP3 */
> +#define R8A7790_CLK_IIC2		0
>  #define R8A7790_CLK_TPU0		4
>  #define R8A7790_CLK_MMCIF1		5
>  #define R8A7790_CLK_SDHI3		11
> @@ -57,6 +58,8 @@
>  #define R8A7790_CLK_SDHI1		13
>  #define R8A7790_CLK_SDHI0		14
>  #define R8A7790_CLK_MMCIF0		15
> +#define R8A7790_CLK_IIC0		18
> +#define R8A7790_CLK_IIC1		23
>  #define R8A7790_CLK_SSUSB		28
>  #define R8A7790_CLK_CMT1		29
>  #define R8A7790_CLK_USBDMAC0		30

-- 
Regards,

Laurent Pinchart

[PATCH 4/5] ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi

[Wolfram Sang]

From: Wolfram Sang <wsa@sang-engineering.com>

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
---
Note: Adding clocks whilst keeping the current sorting is very likely to
break a previously working clock IMO. Imagine adding PCIEC clock inbetween IIC0
and IIC1 here. Adding chronologically and grouped by similar function blocks is
easier to track. An example addition could then look like:

 	R8A7790_CLK_TPU0
 	R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
 	R8A7790_CLK_MMCIF1 R8A7790_CLK_MMCIF0
 	R8A7790_CLK_CMT1
	R8A7790_CLK_IIC2 R8A7790_CLK_IIC1 R8A7790_CLK_IIC0
+	R8A7790_CLK_PCIEC

 arch/arm/boot/dts/r8a7790.dtsi | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index da69afc9e5cb..9e15fb9858e7 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -702,18 +702,19 @@
 		mstp3_clks: mstp3_clks at e615013c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-			clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
-				 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
-				 <&mmc0_clk>, <&rclk_clk>;
+			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
+				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
+				 <&hp_clk>, <&hp_clk>, <&rclk_clk>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
-				R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
-				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
-				R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
+				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
+				R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1
 			>;
 			clock-output-names =
-				"tpu0", "mmcif1", "sdhi3", "sdhi2",
-				"sdhi1", "sdhi0", "mmcif0", "cmt1";
+				"i2c6", "tpu0", "mmcif1", "sdhi3",
+				"sdhi2", "sdhi1", "sdhi0", "mmcif0",
+				"i2c4", "i2c5", "cmt1";
 		};
 		mstp5_clks: mstp5_clks at e6150144 {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -757,16 +758,16 @@
 		mstp9_clks: mstp9_clks at e6150994 {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
-			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
+			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
 				 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
-				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
-				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
-				R8A7790_CLK_I2C0
+				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
+				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
 			>;
 			clock-output-names =
-				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
+				"rcan1", "rcan0", "qspi_mod", "i2c7",
+				"i2c3",	"i2c2", "i2c1", "i2c0";
 		};
 	};
 
-- 
1.9.0

[PATCH 4/5] ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi

[Laurent Pinchart]

Hi Wolfram,

Thank you for the patch.

On Tuesday 11 March 2014 22:24:37 Wolfram Sang wrote:
> From: Wolfram Sang <wsa@sang-engineering.com>
> 
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
> ---
> Note: Adding clocks whilst keeping the current sorting is very likely to
> break a previously working clock IMO. Imagine adding PCIEC clock inbetween
> IIC0 and IIC1 here. Adding chronologically and grouped by similar function
> blocks is easier to track. An example addition could then look like:
> 
>  	R8A7790_CLK_TPU0
>  	R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
>  	R8A7790_CLK_MMCIF1 R8A7790_CLK_MMCIF0
>  	R8A7790_CLK_CMT1
> 	R8A7790_CLK_IIC2 R8A7790_CLK_IIC1 R8A7790_CLK_IIC0
> +	R8A7790_CLK_PCIEC
> 
>  arch/arm/boot/dts/r8a7790.dtsi | 27 ++++++++++++++-------------
>  1 file changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index da69afc9e5cb..9e15fb9858e7 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -702,18 +702,19 @@
>  		mstp3_clks: mstp3_clks at e615013c {
>  			compatible = "renesas,r8a7790-mstp-clocks",
> "renesas,cpg-mstp-clocks";
>  			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
> -			clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
> -				 <&cpg_clocks R8A7790_CLK_SD1>,
> <&cpg_clocks R8A7790_CLK_SD0>,
> -				 <&mmc0_clk>, <&rclk_clk>;
> +			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
> +				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>,
> <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
> +				 <&hp_clk>, <&hp_clk>, <&rclk_clk>;
>  			#clock-cells = <1>;
>  			renesas,clock-indices = <
> -				R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
> -				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
> -				R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
> +				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1
> R8A7790_CLK_SDHI3
> +				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
> R8A7790_CLK_MMCIF0
> +				R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1
> 
>  			>;
> 
>  			clock-output-names =
> -				"tpu0", "mmcif1", "sdhi3", "sdhi2",
> -				"sdhi1", "sdhi0", "mmcif0", "cmt1";
> +				"i2c6", "tpu0", "mmcif1", "sdhi3",
> +				"sdhi2", "sdhi1", "sdhi0", "mmcif0",
> +				"i2c4", "i2c5", "cmt1";

What about calling the clocks iic0-iic2 ?

>  		};
>  		mstp5_clks: mstp5_clks at e6150144 {
>  			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-
clocks";
> @@ -757,16 +758,16 @@
>  		mstp9_clks: mstp9_clks at e6150994 {
>  			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-
clocks";
>  			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
> -			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
> +			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
> <&cp_clk>,
>  				 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
>  			#clock-cells = <1>;
>  			renesas,clock-indices = <
> -				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
> -				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
> -				R8A7790_CLK_I2C0
> +				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
> R8A7790_CLK_IICDVFS
> +				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
> R8A7790_CLK_I2C0
>  			>;
> 
>  			clock-output-names =
> -				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
> +				"rcan1", "rcan0", "qspi_mod", "i2c7",

And iic3 ?

> +				"i2c3",	"i2c2", "i2c1", "i2c0";
>  		};
>  	};

-- 
Regards,

Laurent Pinchart

[PATCH 4/5] ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi

[Magnus Damm]

Hi Wolfram,

On Wed, Mar 12, 2014 at 6:24 AM, Wolfram Sang <wsa@the-dreams.de> wrote:
> From: Wolfram Sang <wsa@sang-engineering.com>
>
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
> ---
> Note: Adding clocks whilst keeping the current sorting is very likely to
> break a previously working clock IMO. Imagine adding PCIEC clock inbetween IIC0
> and IIC1 here. Adding chronologically and grouped by similar function blocks is
> easier to track. An example addition could then look like:
>
>         R8A7790_CLK_TPU0
>         R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
>         R8A7790_CLK_MMCIF1 R8A7790_CLK_MMCIF0
>         R8A7790_CLK_CMT1
>         R8A7790_CLK_IIC2 R8A7790_CLK_IIC1 R8A7790_CLK_IIC0
> +       R8A7790_CLK_PCIEC

Can you please care to explain a bit more about why you see a risk
here? Is it a risk for typo or something else?

It looks to me that this is just a matter about adding the entry at
the right position in several places.

Thanks,

/ magnus

[PATCH 4/5] ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi

[Wolfram Sang]

On Wed, Mar 12, 2014 at 08:05:26PM +0900, Magnus Damm wrote:
> Hi Wolfram,
> 
> On Wed, Mar 12, 2014 at 6:24 AM, Wolfram Sang <wsa@the-dreams.de> wrote:
> > From: Wolfram Sang <wsa@sang-engineering.com>
> >
> > Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
> > ---
> > Note: Adding clocks whilst keeping the current sorting is very likely to
> > break a previously working clock IMO. Imagine adding PCIEC clock inbetween IIC0
> > and IIC1 here. Adding chronologically and grouped by similar function blocks is
> > easier to track. An example addition could then look like:
> >
> >         R8A7790_CLK_TPU0
> >         R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
> >         R8A7790_CLK_MMCIF1 R8A7790_CLK_MMCIF0
> >         R8A7790_CLK_CMT1
> >         R8A7790_CLK_IIC2 R8A7790_CLK_IIC1 R8A7790_CLK_IIC0
> > +       R8A7790_CLK_PCIEC
> 
> Can you please care to explain a bit more about why you see a risk
> here? Is it a risk for typo or something else?

The risk here is if you put something in the "middle" then there is a
chance you might be off, and, for example, mix up parent clocks.
Especially when you need to reformat paragraphs because of too long
lines. Yeah, all this can be avoided by careful review, but this review
really needs to be careful.

> It looks to me that this is just a matter about adding the entry at
> the right position in several places.

Yes. IMO adding it with the pattern I sketched above will make it a
piece of cake since the diff is a lot more simple than the patch I
originally submitted.

That being said, I will keep the current sorting for consistency reasons
but I personally made up my mind ;)

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[PATCH 5/5] ARM: shmobile: r8a7790: add IIC(B) cores to dtsi

[Wolfram Sang]

From: Wolfram Sang <wsa@sang-engineering.com>

Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
---
 arch/arm/boot/dts/r8a7790.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 9e15fb9858e7..5b357480d8bf 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -24,6 +24,10 @@
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
 		spi0 = &qspi;
 		spi1 = &msiof0;
 		spi2 = &msiof1;
@@ -236,6 +240,46 @@
 		status = "disabled";
 	};
 
+	i2c4: i2c at e6500000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+		reg = <0 0xe6500000 0 0x425>;
+		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
+		status = "disabled";
+	};
+
+	i2c5: i2c at e6510000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+		reg = <0 0xe6510000 0 0x425>;
+		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
+		status = "disabled";
+	};
+
+	i2c6: i2c at e6520000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+		reg = <0 0xe6520000 0 0x425>;
+		interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
+		status = "disabled";
+	};
+
+	i2c7: i2c at e60b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+		reg = <0 0xe60b0000 0 0x425>;
+		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
+		status = "disabled";
+	};
+
 	mmcif0: mmcif at ee200000 {
 		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 		reg = <0 0xee200000 0 0x80>;
-- 
1.9.0

[PATCH 5/5] ARM: shmobile: r8a7790: add IIC(B) cores to dtsi

[Laurent Pinchart]

Hi Wolfram,

Thank you for the patch.

On Tuesday 11 March 2014 22:24:38 Wolfram Sang wrote:
> From: Wolfram Sang <wsa@sang-engineering.com>
> 
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
> ---
>  arch/arm/boot/dts/r8a7790.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index 9e15fb9858e7..5b357480d8bf 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -24,6 +24,10 @@
>  		i2c1 = &i2c1;
>  		i2c2 = &i2c2;
>  		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
>  		spi0 = &qspi;
>  		spi1 = &msiof0;
>  		spi2 = &msiof1;
> @@ -236,6 +240,46 @@
>  		status = "disabled";
>  	};
> 
> +	i2c4: i2c at e6500000 {

As for the other patches, iic0-iic3 ?

> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
> +		reg = <0 0xe6500000 0 0x425>;
> +		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
> +		status = "disabled";
> +	};
> +
> +	i2c5: i2c at e6510000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
> +		reg = <0 0xe6510000 0 0x425>;
> +		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
> +		status = "disabled";
> +	};
> +
> +	i2c6: i2c at e6520000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
> +		reg = <0 0xe6520000 0 0x425>;
> +		interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
> +		status = "disabled";
> +	};
> +
> +	i2c7: i2c at e60b0000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
> +		reg = <0 0xe60b0000 0 0x425>;
> +		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
> +		status = "disabled";
> +	};
> +
>  	mmcif0: mmcif at ee200000 {
>  		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
>  		reg = <0 0xee200000 0 0x80>;

-- 
Regards,

Laurent Pinchart

[PATCH 0/5] ARM: shmobile: r8a7790: enable IIC(B) cores

[Laurent Pinchart]

Hi Wolfram,

On Tuesday 11 March 2014 22:24:33 Wolfram Sang wrote:
> This series allows r8a7790 boards to use the alternative IIC(B) controller
> handled by the i2c-sh_mobile driver. Since both i2c cores always use the
> same pins only in a different function group, you can easily use this or
> that core for your devices. For that reason, there is currently no
> enablement on the Lager board, since it needs discussion which core we want
> to have on which bus. sh_mobile seems more stable currently, so I'd vote
> for that.

Do you have a short list of pros and cons from a hardware point of view ?

> Please review and apply if no issues found.
> 
> Thanks,
> 
>    Wolfram
> 
> 
> Wolfram Sang (5):
>   pinctrl: pfc: r8a7790: add i2c0 muxing
>   pinctrl: pfc: r8a7790: add mux data for IIC(B) cores
>   ARM: shmobile: r8a7790: add IIC0-2 clock macros
>   ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi
>   ARM: shmobile: r8a7790: add IIC(B) cores to dtsi
> 
>  arch/arm/boot/dts/r8a7790.dtsi            |  71 +++++++++++++---
>  drivers/pinctrl/sh-pfc/pfc-r8a7790.c      | 136 ++++++++++++++++++++++++++-
>  include/dt-bindings/clock/r8a7790-clock.h |   3 +
>  3 files changed, 196 insertions(+), 14 deletions(-)

-- 
Regards,

Laurent Pinchart

[PATCH 0/5] ARM: shmobile: r8a7790: enable IIC(B) cores

[Wolfram Sang]

> > This series allows r8a7790 boards to use the alternative IIC(B) controller
> > handled by the i2c-sh_mobile driver. Since both i2c cores always use the
> > same pins only in a different function group, you can easily use this or
> > that core for your devices. For that reason, there is currently no
> > enablement on the Lager board, since it needs discussion which core we want
> > to have on which bus. sh_mobile seems more stable currently, so I'd vote
> > for that.
> 
> Do you have a short list of pros and cons from a hardware point of view ?

iic has DMA capability for which we don't have software support yet.
Other than that, I guess it is just details and I haven't looked that deep
into the datasheets yet. That might be coming after this DT enablement.

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