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X-IronPort-AV: E=Sophos;i="5.95,198,1661810400"; d="scan'208";a="26872139" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 20 Oct 2022 13:35:10 +0200 Received: from steina-w.localnet (unknown [10.123.53.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 4EB6B280072; Thu, 20 Oct 2022 13:35:10 +0200 (CEST) From: Alexander Stein To: Andy Chiu Cc: davem@davemloft.net, kuba@kernel.org, michal.simek@xilinx.com, radhey.shyam.pandey@xilinx.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, pabeni@redhat.com, edumazet@google.com, andy.chiu@sifive.com, greentime.hu@sifive.com Subject: Re: [PATCH net-next 1/2] net:xilinx_axi: set mdio frequency according to DT Date: Thu, 20 Oct 2022 13:35:06 +0200 Message-ID: <5953785.aeNJFYEL58@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20221020094106.559266-2-andy.chiu@sifive.com> References: <20221020094106.559266-1-andy.chiu@sifive.com> <20221020094106.559266-2-andy.chiu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_043520_124102_3DD10972 X-CRM114-Status: GOOD ( 27.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Am Donnerstag, 20. Oktober 2022, 11:41:05 CEST schrieb Andy Chiu: > Some FPGA platforms has 80KHz MDIO bus frequency constraint when > conecting Ethernet to its on-board external Marvell PHY. Thus, we may > have to set MDIO clock according to the DT. Otherwise, use the default > 2.5 MHz, as specified by 802.3, if the entry is not present. > > Signed-off-by: Andy Chiu > Reviewed-by: Greentime Hu > --- > .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 25 ++++++++++++++++--- > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c > b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c index > 0b3b6935c558..d07c39d3bcf0 100644 > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c > @@ -18,6 +18,7 @@ > #include "xilinx_axienet.h" > > #define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */ > +#define MDIO_CLK_DIV_MASK 0x3f /* bits[5:0] */ > #define DEFAULT_HOST_CLOCK 150000000 /* 150 MHz */ > > /* Wait till MDIO interface is ready to accept a new transaction.*/ > @@ -155,7 +156,9 @@ static int axienet_mdio_write(struct mii_bus *bus, int > phy_id, int reg, **/ > int axienet_mdio_enable(struct axienet_local *lp) > { > + u32 clk_div; > u32 host_clock; > + u32 mdio_freq; > > lp->mii_clk_div = 0; > > @@ -184,6 +187,13 @@ int axienet_mdio_enable(struct axienet_local *lp) > host_clock); > } > > + if (of_property_read_u32(lp->dev->of_node, "xlnx,mdio-freq", > + &mdio_freq)) { > + mdio_freq = MAX_MDIO_FREQ; > + netdev_info(lp->ndev, "Setting default mdio clock to %u\n", > + mdio_freq); I would opt to print this message only if using non-default frequency. Best regards, Alexander > + } > + > /* clk_div can be calculated by deriving it from the equation: > * fMDIO = fHOST / ((1 + clk_div) * 2) > * > @@ -209,13 +219,20 @@ int axienet_mdio_enable(struct axienet_local *lp) > * "clock-frequency" from the CPU > */ > > - lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; > + clk_div = (host_clock / (mdio_freq * 2)) - 1; > /* If there is any remainder from the division of > - * fHOST / (MAX_MDIO_FREQ * 2), then we need to add > + * fHOST / (mdio_freq * 2), then we need to add > * 1 to the clock divisor or we will surely be above 2.5 MHz > */ > - if (host_clock % (MAX_MDIO_FREQ * 2)) > - lp->mii_clk_div++; > + if (host_clock % (mdio_freq * 2)) > + clk_div++; > + > + /* Check for overflow of mii_clk_div */ > + if (clk_div & ~MDIO_CLK_DIV_MASK) { > + netdev_dbg(lp->ndev, "MDIO clock divisor overflow, setting to maximum > value\n"); + clk_div = MDIO_CLK_DIV_MASK; > + } > + lp->mii_clk_div = (u8)clk_div; > > netdev_dbg(lp->ndev, > "Setting MDIO clock divisor to %u/%u Hz host clock. \n", _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel