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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c4e1a2dsm10921102b3a.44.2026.04.13.02.27.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Apr 2026 02:27:39 -0700 (PDT) Message-ID: <597f5dec-2339-4e12-81fd-d808e6d0d363@oss.qualcomm.com> Date: Mon, 13 Apr 2026 17:27:33 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 16/20] coresight: Add PM callbacks for sink device To: Leo Yan Cc: Suzuki K Poulose , Mike Leach , James Clark , Yeoreum Yun , Mark Rutland , Will Deacon , Yabin Cui , Keita Morisaki , Yuanfang Zhang , Greg Kroah-Hartman , Alexander Shishkin , Tamas Petz , Thomas Gleixner , Peter Zijlstra , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org References: <20260405-arm_coresight_path_power_management_improvement-v10-0-13e94754a8be@arm.com> <20260405-arm_coresight_path_power_management_improvement-v10-16-13e94754a8be@arm.com> <227b77b9-5232-4cff-b26a-458477e9eb32@oss.qualcomm.com> <20260413084833.GA356832@e132581.arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20260413084833.GA356832@e132581.arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDA5MiBTYWx0ZWRfX35KvTp4oc3On eZ3jiJHAA98/K9UqjkJ/+Tpj02RupvWawY3NSP8q3bHLhSBY5Y6Zz0wUel8+gaq2KfJBZR23eY6 DB3XnRUanT4fUNRn7DFcUIR+jxOh7mu/FglNRDeSmVBqLEbQUDSfYPIElAkvhkMl4FOP+vbSW/c Ll7yv0oBMtl89SOCD/GIHD5sv4o/w5x3Br993W3Pv509iDnWc7bCjor3Ago47xp61zVafE7gJ5S YBLiAxZDvIRq5B1u+mPwOix5saYvf6xEQnYfRExR+++798Nw3KrttbwWxweIRe85Of/4mujgjuH XMmog8S0Tei/W0wEFGjs78rUSfnnmLPVJcPLkce9Tu/+8+U1SfvUWV1Y0QFQBLTCXPvnq4fDvXU 3bSADuY3cz6I9qAEgwcqL6Ajc+CCWSteVgiDLNsdiPir08XKw+4PfZFDev/T6Hq2maBnD7myPGy ZfMtsRVlU+LfHjH5bcg== X-Proofpoint-ORIG-GUID: 6epUOIS9Bpg4q40RNmzhyF7Wvcw9RnKs X-Proofpoint-GUID: 6epUOIS9Bpg4q40RNmzhyF7Wvcw9RnKs X-Authority-Analysis: v=2.4 cv=d/LFDxjE c=1 sm=1 tr=0 ts=69dcb70d cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=YxUyXSWcmWsRzNVEdBIA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_02,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 phishscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604130092 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260413_022743_308545_578E4518 X-CRM114-Status: GOOD ( 26.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Leo, On 4/13/2026 4:48 PM, Leo Yan wrote: > On Mon, Apr 13, 2026 at 01:45:50PM +0800, Jie Gan wrote: > > [...] > >>> @@ -1787,15 +1808,32 @@ static int coresight_pm_save(struct coresight_path *path) >>> to = list_prev_entry(coresight_path_last_node(path), link); >>> coresight_disable_path_from_to(path, from, to); >>> + ret = coresight_pm_device_save(coresight_get_sink(path)); >>> + if (ret) >>> + goto sink_failed; >>> + >>> return 0; >>> + >>> +sink_failed: >>> + if (!coresight_enable_path_from_to(path, coresight_get_mode(source), >>> + from, to)) >>> + coresight_pm_device_restore(source); >> >> I have go through the history messages. I have a question about this point >> here: >> >> how can we handle the scenario if coresight_enable_path_from_to failed? It >> means we are never calling coresight_pm_device_restore for the ETM and >> leaving the ETM with OS lock state until CPU reset? > > From a design perspective, if any failure occurs in the idle flow, the > priority is to avoid further mess, especially partial enable/disable > sequences that could lead to lockups. > > The case you mentioned is a typical risk - if a path after source to > sink fails to be enabled, it is unsafe to arbitrarily enable the source > further. We rely on the per-CPU flag "percpu_pm_failed" to disable idle > states, if ETE/TRBE fails to be disabled, if CPU is turned off, this > also might cause lockup. understood. > >> Consider we are calling etm4_disable_hw with OS lock: >> etm4_disable_hw -> etm4_disable_trace_unit -> etm4x_wait_status (may timeout >> here?) > > This is expected. I don't want to introduce a _recovery_ mechanism for > CPU PM failures, which is complex and over-engineering. CPU PM notifier > is low level code, and in my experience, PM issues can be easily > observed once CPU idle is enabled and should be resolved during the > development phase. > > In many cases PM issues are often not caused by CoreSight drivers but by > other modules (e.g., clock or regulator drivers). The log "Failed in > coresight PM save ..." reminds developers the bugs. As said, > percpu_pm_failed is used as a last resort to prevent the platform from > locking up if there is a PM bug. Thanks for the explanation. Thanks, Jie > > Thanks, > Leo