From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BDA8C27C4F for ; Fri, 31 May 2024 13:09:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kGAZZt7k6prRvVToKi1iwIglVteKUTID5Q/l8M1XpcM=; b=h5oQbpJeD1WUm2 +fVacFUhkgMEhz5ltEfpvqsuH44PvfotfFy6d+O+XIfYPTgz3LL2uPv1qpDYgYt0hln2ZAVtaXRvv gbkAWkiOxzEveUGH8mDqMTvWPSqKQn35OsS03nb39FugFx6C6y5xAUmI1yxoZZY0lXcyhbKu3fIJl /JDnFIjLf9H5aZWweoMGv1DrdHXJ7m2m2+fB0XPSQOvlcG3KsXkUnyN0BIpxqgM0iEBdZrxPPM0jl zHuKwyZ0Vy+zc7+cZUiFNLi9xC86FffXAHUzwPc6GBWXtme3utkLkJda2mSdki1E7QZ9rMO0/tD1F BtaIL2jNb4KLIyBr58tQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sD20S-0000000AHoU-2TjJ; Fri, 31 May 2024 13:09:16 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sD20O-0000000AHns-31TG for linux-arm-kernel@lists.infradead.org; Fri, 31 May 2024 13:09:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1717160952; x=1748696952; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cqnIZ10/tMnH14SGwTodwVLTAqEG93IVacBI//NGqKA=; b=SBc/W0/ysj0X5jerhmD2PdcxYTAKdmwhZXaFwrC+szgDcRj+0hlKAG8W e6Bay52l9yluE5kR92/rf+Te1owRitYUtmVtGGgfFjHQ1CRQGYReMqW3b 9BV4sDQXwWhMLppFWipDqYYr2U68NR6ZcaRM3BOTXVqEVf16xM84wsYgp ym3uL9vLPUxZLAKc930AMDEfTeFusBc9ikeh4RELy5qkikyAkFojwcSX7 ja6q9EGGuBqVE0iaD4JryI4hgYD+RAg/WFNwu1+HrZsoTs6MPcHHFYd3n zgIT6HyRdb0pgHXlBFf7i7EhMrUmCFirMBmJeP5rh1sv9SyxCw940UJpi g==; X-CSE-ConnectionGUID: piIEhqDwS3G7ocBCBuNPGg== X-CSE-MsgGUID: /gIAaVxNR4+q09c5pb8i+g== X-IronPort-AV: E=Sophos;i="6.08,204,1712613600"; d="scan'208";a="37161436" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 31 May 2024 15:09:10 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 635101616BC; Fri, 31 May 2024 15:09:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1717160946; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cqnIZ10/tMnH14SGwTodwVLTAqEG93IVacBI//NGqKA=; b=lxByJNjO/QtCEsNdHyiqxj0fDzf7LmTiSAOwv0ZR6WLmbtT5aqEWwnWtaf1kIVISrUh2tS amIhQRmuC41kftsSyNKkfIu6tRQrcoYjFUndRuE805+LJI+u8iEndjTIE9b/zw3s7+Fv8M BwtsZi2lKx3R5yjT3fmS42hLLeJxoD4WDypWrTACgaG4oARBwMsj9Bk1gsDeqYvvbXbI08 PcWwpaEpnV3j+/Z3OUNR4pXkh6JWGckE4C+f83KW0LEf2uy7n/vQR0/ppiuNSb25sCn+f1 Y/PDTIJh4R7WrbQ3sqdU+OLSyz3bGZgoFSmz7CHFatmwU92ygWu4DlXrOLUrhg== From: Alexander Stein To: Esben Haabendal Cc: Shawn Guo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rasmus Villemoes , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: dts: ls1021a: add QUICC Engine node Date: Fri, 31 May 2024 15:09:05 +0200 Message-ID: <5987259.31r3eYUQgx@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <87frtynpfx.fsf@geanix.com> References: <20240530-arm-ls1021a-qe-dts-v1-1-2eda23bdf8c5@geanix.com> <3380831.44csPzL39Z@steina-w> <87frtynpfx.fsf@geanix.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240531_060913_249201_C626A568 X-CRM114-Status: GOOD ( 32.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Esben, Am Freitag, 31. Mai 2024, 14:20:02 CEST schrieb Esben Haabendal: > Alexander Stein writes: > = > > Would you consider current converting into YAML format? > = > You mean converting Documentation/devicetree/bindings/soc/fsl/qe.txt and > Documentation/devicetree/bindings/soc/fsl/qe/*.txt into YAML? > = > I can consider that. I haven't done something like that before, but I > assume it might include some additional work other than trivially format > conversion. So I would prefer to do that after this patch, if that is > ok. Getting the constraints right is probably not that easy. But having verifiable bindinds helps getting the .dtsi right. > > Am Donnerstag, 30. Mai 2024, 16:22:54 CEST schrieb Esben Haabendal: > >> The LS1021A contains a QUICC Engine Block, so add a node to device > >> tree describing that. > >> = > >> Signed-off-by: Esben Haabendal > >> --- > >> arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 51 ++++++++++++++++++++++++++= +++++++++ > >> 1 file changed, 51 insertions(+) > >> = > >> diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts= /nxp/ls/ls1021a.dtsi > >> index e86998ca77d6..ff7be69acdd5 100644 > >> --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi > >> +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi > >> @@ -460,6 +460,57 @@ gpio3: gpio@2330000 { > >> #interrupt-cells =3D <2>; > >> }; > >> = > >> + uqe: uqe@2400000 { > >> + #address-cells =3D <1>; > >> + #size-cells =3D <1>; > >> + device_type =3D "qe"; > >> + compatible =3D "fsl,qe", "simple-bus"; > >> + ranges =3D <0x0 0x0 0x2400000 0x40000>; > >> + reg =3D <0x0 0x2400000 0x0 0x480>; > > > > Properties please in this order: > > * compatible > > * reg > > * #address-cells > > * #size-cells > > * ranges > > * device_type > = > Fixing. > = > >> + brg-frequency =3D <150000000>; > >> + bus-frequency =3D <300000000>; > > > > Mh, aren't these values depending on your actual RCW configuration? > = > Yes, you are right. The QE bus-frequency comes from platform_clk which > is controlled by various bits in RCW and sys_ref_clk. > = > So I guess it should be possible to derive bus-frequency from sysclk > clock-frequency attribute and RCW. But fsl,qe bus-frequency is a > required property... > = > Max bus-frequency for LS1021A is 300 MHz. But it should be possible to > set it lower, although I suspect that many/most/everyone is running it > at 300 MHz. Thanks for confirmation. I'll let DT maintainer decide how to deal with thi= s. > >> + fsl,qe-num-riscs =3D <1>; > >> + fsl,qe-num-snums =3D <28>; > > > > Current bindings defines: > >> fsl,qe-snums: This property has to be specified as '/bits/ 8' value, > >> defining the array of serial number (SNUM) values for the virtual > >> threads. > > > > So '/bits/ 8' is missing. > = > Ok, so you want me to add an array for fs,qe-snums attribute? > None of the existing fsl,qe devices has a fsl,qe-snums. > And qe_snums_init() has a fallback, so I don't think it is correct to > specify fsl,qe-snums to be a required property in the bindings. It > should be listed as optional. fsl,qe-num-snums is a deprecated property, so IMHO the replacement fsl,qe-snums should be used instead for new device tree entries. qe_snums_init() supporting 'fsl,qe-num-snums' is just to support "legacy bindings" as stated in the comment. > = > >> + qeic: qeic@80 { > >> + compatible =3D "fsl,qe-ic"; > >> + reg =3D <0x80 0x80>; > >> + #address-cells =3D <0>; > >> + interrupt-controller; > >> + #interrupt-cells =3D <1>; > >> + interrupts =3D >> + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > >> + }; > >> + > >> + ucc@2000 { > >> + cell-index =3D <1>; > >> + reg =3D <0x2000 0x200>; > >> + interrupts =3D <32>; > >> + interrupt-parent =3D <&qeic>; > > > > Move cell-index to last position. > = > Done. > = > >> + }; > >> + > >> + ucc@2200 { > >> + cell-index =3D <3>; > >> + reg =3D <0x2200 0x200>; > >> + interrupts =3D <34>; > >> + interrupt-parent =3D <&qeic>; > > > > Same here. > = > Done. > = > >> + }; > >> + > >> + muram@10000 { > >> + #address-cells =3D <1>; > >> + #size-cells =3D <1>; > >> + compatible =3D "fsl,qe-muram", "fsl,cpm-muram"; > >> + ranges =3D <0x0 0x10000 0x6000>; > > > > Node address but no 'reg' property? I have no idea if this is okay. > > Also compatible (and possibly reg) first. > = > It is done in the same way for all existing fsl,qe-muram devices. So if > it is not okay, a tree-wide fixup would be in place. I can't finally say if this is okay, but at least the compatible shall be listed first. Thanks and best regards, Alexander -- = TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel