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From: james.morse@arm.com (James Morse)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 04/13] arm64: kernel: Survive corrected RAS errors notified by SError
Date: Fri, 05 Jan 2018 18:28:29 +0000	[thread overview]
Message-ID: <5A4FC3CD.3030809@arm.com> (raw)
In-Reply-To: <43942acd-f6ff-ec58-aafb-a6f3ba40fab9@huawei.com>

Hi gengdongjiu,

On 16/12/17 02:53, gengdongjiu wrote:
> 
> On 2017/12/15 23:50, James Morse wrote:
>> +asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
>> +{
>> +	nmi_enter();
> 
>         How about firstly let APEI kernel driver to handle it by adding patch[1]? if the handling is successful, do_serror() direct return;
>         Otherwise continue check the ESR value, for example:
> 	if (!ghes_notify_sei())
> 		return;

This is where I think we will end up. Adding that could should be part of a
future firmware-first series.
We can't do it until APEI can share its in_nmi() path with multiple users. (what
happens if we take an SError while handling an NOTIFY_SEA).

I still haven't managed to get the RFC of what I think is required out.
(I need this for SDEI too),


>> +
>> +	/* non-RAS errors are not containable */
>> +	if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
>> +		arm64_serror_panic(regs, esr);
>>  
>> -	panic("Asynchronous SError Interrupt");
>> +	nmi_exit();
>>  }


Thanks,

James

  reply	other threads:[~2018-01-05 18:28 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-15 15:50 [PATCH v5 00/13] arm64/KVM: RAS & IESB for firmware first support James Morse
2017-12-15 15:50 ` [PATCH v5 01/13] arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early James Morse
2017-12-15 16:24   ` Suzuki K Poulose
2017-12-15 15:50 ` [PATCH v5 02/13] arm64: sysreg: Move to use definitions for all the SCTLR bits James Morse
2017-12-15 15:50 ` [PATCH v5 03/13] arm64: cpufeature: Detect CPU RAS Extentions James Morse
2017-12-15 15:50 ` [PATCH v5 04/13] arm64: kernel: Survive corrected RAS errors notified by SError James Morse
2017-12-16  2:53   ` gengdongjiu
2018-01-05 18:28     ` James Morse [this message]
2017-12-16  4:08   ` gengdongjiu
2017-12-16  4:51     ` gengdongjiu
2018-01-05 18:28       ` James Morse
2017-12-15 15:50 ` [PATCH v5 05/13] arm64: Unconditionally enable IESB on exception entry/return for firmware-first James Morse
2017-12-15 15:50 ` [PATCH v5 06/13] arm64: kernel: Prepare for a DISR user James Morse
2017-12-15 15:50 ` [PATCH v5 07/13] KVM: arm/arm64: mask/unmask daif around VHE guests James Morse
2018-01-08 16:26   ` James Morse
2017-12-15 15:50 ` [PATCH v5 08/13] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2 James Morse
2017-12-15 15:50 ` [PATCH v5 09/13] KVM: arm64: Save/Restore guest DISR_EL1 James Morse
2017-12-15 15:50 ` [PATCH v5 10/13] KVM: arm64: Save ESR_EL2 on guest SError James Morse
2017-12-15 15:50 ` [PATCH v5 11/13] KVM: arm64: Handle RAS SErrors from EL1 on guest exit James Morse
2017-12-15 15:51 ` [PATCH v5 12/13] KVM: arm64: Handle RAS SErrors from EL2 " James Morse
2017-12-15 15:51 ` [PATCH v5 13/13] KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA James Morse
2018-01-08 16:27   ` James Morse

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