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Mon, 06 Jan 2025 05:45:11 -0800 (PST) Received: from smtpclient.apple ([87.200.95.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c8474c2sm47324663f8f.55.2025.01.06.05.45.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Jan 2025 05:45:11 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.200.121\)) Subject: Re: [RFC PATCH v1 2/2] iio: adc: meson: add support for the GXLX SoC From: Christian Hewitt In-Reply-To: Date: Mon, 6 Jan 2025 17:44:56 +0400 Cc: Jonathan Cameron , linux-amlogic@lists.infradead.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, gnstark@salutedevices.com, lars@metafoo.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <5CEDC847-2653-42F3-A85E-A06D6E5DB135@gmail.com> References: <20241231194207.2772750-1-martin.blumenstingl@googlemail.com> <20241231194207.2772750-3-martin.blumenstingl@googlemail.com> <20250104135912.390ec87c@jic23-huawei> To: Martin Blumenstingl X-Mailer: Apple Mail (2.3826.200.121) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250106_054514_438506_E9DE6726 X-CRM114-Status: GOOD ( 25.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > On 5 Jan 2025, at 7:49=E2=80=AFpm, Martin Blumenstingl = wrote: >=20 > Hi Jonathan, >=20 > On Sat, Jan 4, 2025 at 2:59=E2=80=AFPM Jonathan Cameron = wrote: >>=20 >> On Tue, 31 Dec 2024 20:42:07 +0100 >> Martin Blumenstingl wrote: >>=20 >>> The SARADC IP on the GXLX SoC itself is identical to the one found = on >>> GXL SoCs. However, GXLX SoCs require poking the first three bits in = the >>> MESON_SAR_ADC_REG12 register to get the three MPLL clocks (used as = clock >>> generators for the audio frequencies) to work. >>>=20 >>> The reason why there are MPLL clock bits in the ADC register space = is >>> entirely unknown and it seems that nobody is able to comment on = this. >>> So clearly mark this as a workaround and add a warning so users are >>> notified that this workaround can change (once we know what these = bits >>> actually do). >>=20 >> So IIUC this is to make some non ADC component work. > That's correct >=20 >> How are you handling dependencies? The ADC driver might not be = loaded or >> is there some reason it definitely is at the point where the audio = driver >> loads? > Unfortunately there are no dependencies at the moment. > To me it's not even 100% clear if those bits are a dependency for the > audio IP or if they are instead linked with the clock controller (more > background info: some of the MPLL clocks are - at least in theory, in > practice we don't use that - are also used as input for the Mali GPU > and video subsystem. The only practical usage that I'm aware of is the > audio controller). In my testing it makes no difference to the audio driver when the adc bit poke is done. The audio driver probes and loads and you can play media without generating any visible errors. There=E2=80=99s just no = audible output on GXLX until the poke - it=E2=80=99s like hitting an un-mute = button. For the series: Tested-by: Christian Hewitt Christian > Christian and I have both tried with all of our contacts at Amlogic > but did not get any answers. > If I knew the purpose of these bits I'd model them as whatever they > are (resets, clock gates, ...) and provide proper dt-bindings. >=20 >=20 > Best regards, > Martin