From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0926C52D7C for ; Fri, 9 Aug 2024 14:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version: Content-Transfer-Encoding:Content-Type:In-Reply-To:References:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=LwbwJExb4fR8nP6kQhuPf7fviAdv8IGlMky130ndRSo=; b=eCi00pBPLLv8MvAfn3aOBizAbg k8huDqWlN0WNT1azfmNYyzd18vKE0Ag7NxO0R46blswRLxj1ASKi2RGi+FSxhN3LyVx3kqyX23dfm aI5NzNfz7B8l4FHzzSSn+QGWaPv5mYDDkEN1ETSybvbTqupRTrkoqVEtxUqAVYa13y3FoWhuYL+RI 4vYBJXbeNnT63XQznYJMSU05lJV8huMTcmhLi17kvGPzTM6UCTjoh4T7MrZPH9zt34LDotnfyd04l VMw3xbPm1Xh6/cVZibO2MwpMqx6Hz49mpN45uNdCWhoMoz3Az/STQckMQggYpeBLStyIyQBbh9LFa 6klHhMXw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1scQa7-0000000BXJm-40vG; Fri, 09 Aug 2024 14:27:03 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1scQZX-0000000BXEC-1WiX for linux-arm-kernel@lists.infradead.org; Fri, 09 Aug 2024 14:26:29 +0000 Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4WgR1628Bqz1S76l; Fri, 9 Aug 2024 22:21:30 +0800 (CST) Received: from dggpemf500002.china.huawei.com (unknown [7.185.36.57]) by mail.maildlp.com (Postfix) with ESMTPS id 626F818002B; Fri, 9 Aug 2024 22:26:16 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (7.191.163.240) by dggpemf500002.china.huawei.com (7.185.36.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 9 Aug 2024 22:26:15 +0800 Received: from lhrpeml500005.china.huawei.com ([7.191.163.240]) by lhrpeml500005.china.huawei.com ([7.191.163.240]) with mapi id 15.01.2507.039; Fri, 9 Aug 2024 15:26:13 +0100 From: Shameerali Kolothum Thodi To: Jason Gunthorpe , "acpica-devel@lists.linux.dev" , Alex Williamson , "Guohanjun (Hanjun Guo)" , "iommu@lists.linux.dev" , Joerg Roedel , Kevin Tian , "kvm@vger.kernel.org" , "Len Brown" , "linux-acpi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Lorenzo Pieralisi , "Rafael J. Wysocki" , "Robert Moore" , Robin Murphy , "Sudeep Holla" , Will Deacon CC: Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , "patches@lists.linux.dev" Subject: RE: [PATCH 2/8] iommu/arm-smmu-v3: Use S2FWB when available Thread-Topic: [PATCH 2/8] iommu/arm-smmu-v3: Use S2FWB when available Thread-Index: AQHa6FotZjxW0m4zQk+YUXvVQrNfTbIe/kcw Date: Fri, 9 Aug 2024 14:26:13 +0000 Message-ID: <5af45a0c060c487fb41983c434de0ec6@huawei.com> References: <0-v1-54e734311a7f+14f72-smmuv3_nesting_jgg@nvidia.com> <2-v1-54e734311a7f+14f72-smmuv3_nesting_jgg@nvidia.com> In-Reply-To: <2-v1-54e734311a7f+14f72-smmuv3_nesting_jgg@nvidia.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.203.177.241] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240809_072627_759828_45AE5D93 X-CRM114-Status: GOOD ( 19.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Jason Gunthorpe > Sent: Wednesday, August 7, 2024 12:41 AM > To: acpica-devel@lists.linux.dev; Alex Williamson > ; Guohanjun (Hanjun Guo) > ; iommu@lists.linux.dev; Joerg Roedel > ; Kevin Tian ; kvm@vger.kernel.org= ; > Len Brown ; linux-acpi@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; Lorenzo Pieralisi ; Ra= fael J. > Wysocki ; Robert Moore ; Robin > Murphy ; Sudeep Holla ; > Will Deacon > Cc: Eric Auger ; Jean-Philippe Brucker philippe@linaro.org>; Moritz Fischer ; Michael Shavit > ; Nicolin Chen ; > patches@lists.linux.dev; Shameerali Kolothum Thodi > > Subject: [PATCH 2/8] iommu/arm-smmu-v3: Use S2FWB when available >=20 > Force Write Back (FWB) changes how the S2 IOPTE's MemAttr field > works. When S2FWB is supported and enabled the IOPTE will force cachable > access to IOMMU_CACHE memory and deny cachable access otherwise. >=20 > This is not especially meaningful for simple S2 domains, it apparently > doesn't even force PCI no-snoop access to be coherent. >=20 > However, when used with a nested S1, FWB has the effect of preventing the > guest from choosing a MemAttr that would cause ordinary DMA to bypass the > cache. Consistent with KVM we wish to deny the guest the ability to becom= e > incoherent with cached memory the hypervisor believes is cachable so we > don't have to flush it. >=20 > Turn on S2FWB whenever the SMMU supports it and use it for all S2 > mappings. >=20 > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 ++++++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ > drivers/iommu/io-pgtable-arm.c | 24 +++++++++++++++++---- > include/linux/io-pgtable.h | 2 ++ > 4 files changed, 31 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 531125f231b662..7fe1e27d11586c 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1612,6 +1612,8 @@ void arm_smmu_make_s2_domain_ste(struct > arm_smmu_ste *target, > FIELD_PREP(STRTAB_STE_1_EATS, > ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0)); >=20 > + if (smmu->features & ARM_SMMU_FEAT_S2FWB) > + target->data[1] |=3D cpu_to_le64(STRTAB_STE_1_S2FWB); > if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) > target->data[1] |=3D > cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, >=20 > STRTAB_STE_1_SHCFG_INCOMING)); > @@ -2400,6 +2402,8 @@ static int arm_smmu_domain_finalise(struct > arm_smmu_domain *smmu_domain, > pgtbl_cfg.oas =3D smmu->oas; > fmt =3D ARM_64_LPAE_S2; > finalise_stage_fn =3D arm_smmu_domain_finalise_s2; > + if (smmu->features & ARM_SMMU_FEAT_S2FWB) > + pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_S2FWB; This probably requires an update in arm_64_lpae_alloc_pgtable_s2() quirks c= heck. Thanks, Shameer