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Tue, 18 Feb 2025 11:01:45 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D07F540046; Tue, 18 Feb 2025 11:00:29 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6E8D73AF671; Tue, 18 Feb 2025 10:58:23 +0100 (CET) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 18 Feb 2025 10:58:22 +0100 Message-ID: <5dde0e21-eddb-4bbf-a246-a2760792eb59@foss.st.com> Date: Tue, 18 Feb 2025 10:58:22 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/8] dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller To: Krzysztof Kozlowski CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Philipp Zabel , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon , , , , , , References: <20250210131826.220318-1-patrice.chotard@foss.st.com> <20250210131826.220318-4-patrice.chotard@foss.st.com> <20250213-adorable-conscious-pogona-4114cf@krzk-bin> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: <20250213-adorable-conscious-pogona-4114cf@krzk-bin> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.87.62] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_03,2025-02-18_01,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250218_020205_979457_4F307C21 X-CRM114-Status: GOOD ( 21.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2/13/25 09:00, Krzysztof Kozlowski wrote: > On Mon, Feb 10, 2025 at 02:18:21PM +0100, patrice.chotard@foss.st.com wrote: >> From: Patrice Chotard >> >> Add bindings for STM32 Octo Memory Manager (OMM) controller. >> >> OMM manages: >> - the muxing between 2 OSPI busses and 2 output ports. >> There are 4 possible muxing configurations: >> - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 >> output is on port 2 >> - OSPI1 and OSPI2 are multiplexed over the same output port 1 >> - swapped mode (no multiplexing), OSPI1 output is on port 2, >> OSPI2 output is on port 1 >> - OSPI1 and OSPI2 are multiplexed over the same output port 2 >> - the split of the memory area shared between the 2 OSPI instances. >> - chip select selection override. >> - the time between 2 transactions in multiplexed mode. >> >> Signed-off-by: Patrice Chotard >> --- >> .../memory-controllers/st,stm32mp25-omm.yaml | 201 ++++++++++++++++++ >> 1 file changed, 201 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml >> new file mode 100644 >> index 000000000000..c897e6bf490d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml >> @@ -0,0 +1,201 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STM32 Octo Memory Manager (OMM) >> + >> +maintainers: >> + - Patrice Chotard >> + >> +description: | >> + The STM32 Octo Memory Manager is a low-level interface that enables an >> + efficient OCTOSPI pin assignment with a full I/O matrix (before alternate >> + function map) and multiplex of single/dual/quad/octal SPI interfaces over >> + the same bus. It Supports up to: >> + - Two single/dual/quad/octal SPI interfaces >> + - Two ports for pin assignment >> + >> +properties: >> + compatible: >> + const: st,stm32mp25-omm >> + >> + "#address-cells": >> + const: 2 >> + >> + "#size-cells": >> + const: 1 >> + >> + ranges: >> + description: | >> + Reflects the memory layout with four integer values per OSPI instance. >> + Format: >> + 0 >> + minItems: 2 >> + maxItems: 2 >> + >> + reg: >> + items: >> + - description: OMM registers >> + - description: OMM memory map area >> + >> + reg-names: >> + items: >> + - const: regs >> + - const: memory_map >> + >> + memory-region: >> + description: | >> + Memory region shared between the 2 OCTOSPI instance. >> + One or two phandle to a node describing a memory mapped region >> + depending of child number. >> + minItems: 1 >> + maxItems: 2 >> + >> + memory-region-names: >> + description: | >> + OCTOSPI instance's name to which memory region is associated >> + items: >> + enum: [ospi1, ospi2] >> + minItems: 1 >> + maxItems: 2 >> + >> + clocks: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + access-controllers: >> + maxItems: 1 >> + >> + st,syscfg-amcr: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + description: | >> + The Address Mapping Control Register (AMCR) is used to split the 256MB >> + memory map area shared between the 2 OSPI instance. The Octo Memory >> + Manager sets the AMCR depending of the memory-region configuration. >> + The memory split bitmask description is: >> + - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped >> + - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes) >> + - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes) >> + - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes) >> + - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes) >> + items: >> + - description: phandle to syscfg >> + - description: register offset within syscfg >> + - description: register bitmask for memory split >> + >> + st,omm-req2ack-ns: >> + description: | >> + In multiplexed mode (MUXEN = 1), this field defines the time in >> + nanoseconds between two transactions. > > default: ? Yes, i will add the default value > >> + >> + st,omm-cssel-ovr: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: | >> + Configure the chip select selector override for the 2 OCTOSPIs. >> + - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1 >> + - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1 >> + - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2 >> + - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2 >> + minimum: 0 >> + maximum: 3 > > default: ? ditto > >> + >> + st,omm-mux: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: | >> + Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports. >> + - 0: direct mode, default > > Don't repeat constraints in free form text. > ok >> + - 1: mux OCTOSPI1 and OCTOSPI2 to port 1 >> + - 2: swapped mode >> + - 3: mux OCTOSPI1 and OCTOSPI2 to port 2 >> + minimum: 0 >> + maximum: 3 > > default: ? i will add the default value as well Thanks Patrice > > None of them are required, so usually we expect defaults. > > Reviewed-by: Krzysztof Kozlowski > > Best regards, > Krzysztof >