From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F0AEC982FA for ; Wed, 23 Sep 2026 09:20:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=F7smFy3SJHZMNMinsVMH1cEbEK3TII5c2U/nO1XFx3w=; b=xtfQtaUvUo7+8BrKFPnD3b3cEx tjT1jNRhmCJKS0P8D/1M9F+c1L70IWVdUqV5VDOZDpA8EbKfYoVKTMtFQf+foZhDKSDrlNteFegP+ 4ABvWvQjCq7MXhVfD2IX/IbIqMvGlLBQMD7H0iyBnBEBNl8E9Wtup2hSpNLMCwp+yhFdV2aw2JBhB wN6eqIk4Z3BmZIDQZZeFX8CLCuyRXEhkIXXzIcx9DaNIBGmyRCbiAWS37qaHC2w7LMZXHNOTp9KPC PneNBUHonXImLAYlkuiP4VYSgXMLzGekmmPgqOWNkEIYfj+avYj0ptmnsyBSgObPbnuGIjp51R84W mruqgMUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x9J9L-00000007iLZ-0n4D; Wed, 23 Sep 2026 09:20:23 +0000 Received: from out-170.mta0.migadu.com ([2001:41d0:1004:224b::aa] helo=mta0.migadu.com) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1x9J9I-00000007iL1-3Mhl for linux-arm-kernel@lists.infradead.org; Wed, 23 Sep 2026 09:20:22 +0000 X-Envelope-To: linux-arm-kernel@lists.infradead.org DKIM-Signature: a=rsa-sha256; bh=YMhS+fdcs05Fz41Krh16jBe0uGQOm1VcPnksCJC5d8Y=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1790155217; v=1; x=1790760017; b=jJT0I39bXhD6GU542Mp5YztveUpOS93TC4EEHgwU2Okkw7FLq2uBTlIzeyezcRNEuejK+v5O q+5pMywxK7aEqraBNCG8JCiMSTgtns0MV7S1dh9GE0TCnjxinBkQgNnBvMlv0oRUmmhmKCEZjgj 9sqEyVbkJH6K2Kn8T5AZq9xw= X-Envelope-To: linux-arm-kernel@lists.infradead.org Received: by smtp.migadu.com with ESMTPS id 78a4c3ba66ae85bc; Wed, 23 Sep 2026 09:20:15 +0000 X-Mizu-Trace-ID: 78a4c3ba66ae85bc X-Migadu-Flow: FLOW_OUT Message-ID: <5e42a314-41f6-484a-8c3d-c913b5405889@linux.dev> Date: Wed, 23 Sep 2026 17:20:10 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] irqchip/gic: Fix UBSAN shift-out-of-bounds in GIC helpers To: Zhu Ling Cc: maz@kernel.org, tglx@kernel.org, radu@rendec.net, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <6b668efe-ef7a-474a-957c-893755ebba46@linux.dev> <20260923082804.13197-1-zhuling2709@phytium.com.cn> Content-Language: en-US From: Zenghui Yu In-Reply-To: <20260923082804.13197-1-zhuling2709@phytium.com.cn> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260923_022020_985514_14FB7D9C X-CRM114-Status: GOOD ( 15.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/23/26 4:28 PM, Zhu Ling wrote: > When running with UBSAN enabled, enabling a GPIO controller that uses a > GIC interrupt as its parent triggers several shift-out-of-bounds warnings: > > shift-out-of-bounds in drivers/irqchip/irq-gic-common.c:50:21 > left shift of 2 by 30 places cannot be represented in type 'int' > > Similar reports are emitted from gic_poke_irq() and gic_peek_irq() in > drivers/irqchip/irq-gic-v3.c. The corresponding GICv2 helpers use the > same signed-shift pattern. These masks are generated by shifting signed > integer constants, which invokes undefined behavior when bit 31 is > selected. > > Use BIT() to generate the masks with an unsigned type and make their > intent explicit. > > Signed-off-by: Zhu Ling > --- > Changes in v3: > - Fix the same issue in the GICv2 gic_poke_irq() and gic_peek_irq() > helpers, as pointed out by Zenghui. > > Changes in v2: > - Use BIT() instead of explicit unsigned shifts, as suggested by Marc. > - Drop the redundant introductory text from the email. > - Update the author email address. > > Link: https://lore.kernel.org/r/2fJDwUUYdEf2_eaRa041L9xkT8RkSWFeo7euOnqMbbPhUatLlEaAvGfB6sOspDmXaxO87Eh7bQLV9UolyjbMtZBT1wB2UGypjPOo0Z-RC0Q=@proton.me > --- > drivers/irqchip/irq-gic-common.c | 2 +- > drivers/irqchip/irq-gic-v3.c | 4 ++-- > drivers/irqchip/irq-gic.c | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) Looks good, Reviewed-by: Zenghui Yu (Huawei) Thanks, Zenghui